SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
13.7.5.3.3.5 Operation Sequence
Figure 13-5, Figure 13-6, and Figure 13-7 show several operation sequences that can be used to operate the PKA engine. Interface bus transactions and the behavior of the main interrupt output (bit [1] of the interrupt output bus) are described in a stylized way.
The left side of the sequence shown in Figure 13-5 shows the start-up behavior. The interrupt is inactive (low) during module reset and active (high) within 10 module clock cycles after starting the sequencer program. In the case where a program ROM is used, the sequencer is started immediately when the module reset is released. For program RAM-equipped engines, the sequencer firmware must first be loaded, and then the sequencer must be taken out of reset (write 0b to bit [31] of the PKA_SEQ_CTRL register) to start the sequencer program.
The right side of Figure 13-5 shows the normal operation sequence. A normal operation sequence begins by writing input vectors in the PKA data RAM and vector pointers and length values to the PKA engine control registers (can be completed in any order). The operation is started with a write to the PKA_FUNCTION register, which results in dropping the main interrupt output inactive within two clock cycles after setting the RUN bit. When the PKA engine has finished executing the requested operation, the main interrupt is activated again and the result status can be read from the status registers (if needed). The result vector or vectors can be read from the PKA data RAM.
Figure 13-5 Operation Sequence
Figure 13-6 shows a more optimized, interleaved operation sequence. When enough PKA data RAM is available, separate areas in the RAM can be used for interleaving the input vector writes and result vector reads. The input vectors (for the second operation) are written while the first operation is in execution. Writing of the pointer and length registers and actual starting of the second command is done before the result vectors of the first command are read from the PKA data RAM. Writing the input vectors for a third operation can be done immediately following the reading of the first result, all while the second operation is in execution.
Figure 13-6 Interleaved Operation SequenceFigure 13-7 shows a highly optimized, basic PKCP operation sequence. For basic PKCP operations, the vector pointer and length registers are double buffered; they may be written while an operation is in progress. This ability allows a more optimized interleaving of bus accesses with writing the vectors and pointer and length register for the second operation while the first operation is in execution. When the interrupt activation occurs, only the command of the second operation is required for start-up.
Figure 13-7 also shows that the status of the first operation is read after the second command is started; to make sure this status is not changed by an early completion of the second operation, the second operation must be started with the Stall Result bit (bit [24] of the PKA_FUNCTION register) written as 1b. After reading the status, the Stall Result bit must be reset to allow updating of the status. If the first operation has no status to check, setting the Stall Result bit is not required.
Figure 13-7 Basic PKCP Operation Sequence