SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
#UART_PL011_R1P5_UART_PL011_R1P5_MAP1_TABLE_1 lists the memory-mapped registers for the UART registers. All register offset addresses not listed in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
Complex bit access types are encoded to fit into small table cells. #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_LEGEND shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
DR is shown in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_DR_FIGURE and described in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_DR_TABLE.
Return to the Summary Table.
Data
For
words to be transmitted:
- if the FIFOs are enabled
(LCRH.FEN = 1), data written to this location is pushed onto the transmit FIFO
- if the FIFOs are not enabled (LCRH.FEN = 0), data
is stored in the transmitter holding register (the bottom word of the transmit
FIFO).
The write operation initiates transmission
from the UART. The data is prefixed with a start bit, appended with the appropriate
parity bit (if parity is enabled), and a stop bit.
The
resultant word is then transmitted.
For received
words:
- if the FIFOs are enabled (LCRH.FEN = 1),
the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed
onto the 12-bit wide receive FIFO
- if the FIFOs are
not enabled (LCRH.FEN = 0), the data byte and status are stored in the receiving
holding register (the bottom word of the receive FIFO).
The received data byte is read by performing reads from this register along with
the corresponding status information. The status information can also be read by a
read of the RSR register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-0h | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | OE | BE | PE | FE | DATA | ||||||||||
| R-0h | R-X | R-X | R-X | R-X | R/W-X | ||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-12 | RESERVED | R | 0h | Reserved |
| 11 | OE | R | X | UART Overrun Error: This bit is set to 1 if data is received and the receive FIFO is already full. The FIFO contents remain valid because no more data is written when the FIFO is full, , only the contents of the shift register are overwritten. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. |
| 10 | BE | R | X | UART Break Error: This bit is set to 1 if a break condition was detected, indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO (that is., the oldest received data character since last read). When a break occurs, a 0 character is loaded into the FIFO. The next character is enabled after the receive data input (UARTRXD input pin) goes to a 1 (marking state), and the next valid start bit is received. |
| 9 | PE | R | X | UART Parity Error: When set to 1, it indicates that the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select. In FIFO mode, this error is associated with the character at the top of the FIFO (that is, the oldest received data character since last read). |
| 8 | FE | R | X | UART Framing Error: When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO (that is., the oldest received data character since last read). |
| 7-0 | DATA | R/W | X | Data transmitted or received: On writes, the transmit data character is pushed into the FIFO. On reads, the oldest received data character since the last read is returned. |
RSR is shown in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_RSR_FIGURE and described in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_RSR_TABLE.
Return to the Summary Table.
Status
This register is mapped to the same address as ECR register. Reads from this
address are associated with RSR register and return the receive status. Writes to
this address are associated with ECR register and clear the receive status flags
(framing, parity, break, and overrun errors).
If the
status is read from this register, then the status information for break, framing
and parity corresponds to the data character read from the Data Register, DR prior
to reading the RSR. The status information for overrun is set immediately when an
overrun condition occurs.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-0h | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | OE | BE | PE | FE | |||||||||||
| R-0h | R-0h | R-0h | R-0h | R-0h | |||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-4 | RESERVED | R | 0h | Reserved |
| 3 | OE | R | 0h | UART Overrun Error: This bit is set to 1 if data is received and the receive FIFO is already full. The FIFO contents remain valid because no more data is written when the FIFO is full, , only the contents of the shift register are overwritten. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. |
| 2 | BE | R | 0h | UART Break Error: This bit is set to 1 if a break condition was detected, indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). When a break occurs, a 0 character is loaded into the FIFO. The next character is enabled after the receive data input (UARTRXD input pin) goes to a 1 (marking state), and the next valid start bit is received. |
| 1 | PE | R | 0h | UART Parity Error: When set to 1, it indicates that the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select. |
| 0 | FE | R | 0h | UART Framing Error: When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). |
ECR is shown in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_ECR_FIGURE and described in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_ECR_TABLE.
Return to the Summary Table.
Error Clear
This register is mapped to the same address as RSR
register. Reads from this address are associated with RSR register and return the
receive status. Writes to this address are associated with ECR register and clear
the receive status flags (framing, parity, break, and overrun errors).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-0h | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | OE | BE | PE | FE | |||||||||||
| R-0h | W-0h | W-0h | W-0h | W-0h | |||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-4 | RESERVED | R | 0h | Reserved |
| 3 | OE | W | 0h | The framing (FE), parity (PE), break (BE) and overrun (OE) errors are cleared to 0 by any write to this register. |
| 2 | BE | W | 0h | The framing (FE), parity (PE), break (BE) and overrun (OE) errors are cleared to 0 by any write to this register. |
| 1 | PE | W | 0h | The framing (FE), parity (PE), break (BE) and overrun (OE) errors are cleared to 0 by any write to this register. |
| 0 | FE | W | 0h | The framing (FE), parity (PE), break (BE) and overrun (OE) errors are cleared to 0 by any write to this register. |
FR is shown in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_FR_FIGURE and described in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_FR_TABLE.
Return to the Summary Table.
Flag
Reads from this register return the UART flags.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TXFE | RXFF | TXFF | RXFE | BUSY | RESERVED | CTS | |
| R-1h | R-0h | R-0h | R-1h | R-0h | R-0h | R-X | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R | 0h | Reserved |
| 7 | TXFE | R | 1h | UART Transmit FIFO Empty: The meaning of this bit depends on the state of LCRH.FEN . - If the FIFO is disabled, this bit is set when the transmit holding register is empty. - If the FIFO is enabled, this bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. |
| 6 | RXFF | R | 0h | UART Receive FIFO Full: The meaning of this bit depends on the state of LCRH.FEN. - If the FIFO is disabled, this bit is set when the receive holding register is full. - If the FIFO is enabled, this bit is set when the receive FIFO is full. |
| 5 | TXFF | R | 0h | UART Transmit FIFO Full: Transmit FIFO full. The meaning of this bit depends on the state of LCRH.FEN. - If the FIFO is disabled, this bit is set when the transmit holding register is full. - If the FIFO is enabled, this bit is set when the transmit FIFO is full. |
| 4 | RXFE | R | 1h | UART Receive FIFO Empty: Receive FIFO empty. The meaning of this bit depends on the state of LCRH.FEN. - If the FIFO is disabled, this bit is set when the receive holding register is empty. - If the FIFO is enabled, this bit is set when the receive FIFO is empty. |
| 3 | BUSY | R | 0h | UART Busy: If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. |
| 2-1 | RESERVED | R | 0h | Reserved |
| 0 | CTS | R | X | Clear To Send: This bit is the complement of the active-low UART CTS input pin. That is, the bit is 1 when CTS input pin is LOW. |
IBRD is shown in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_IBRD_FIGURE and described in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_IBRD_TABLE.
Return to the Summary Table.
Integer Baud-Rate Divisor
If this register is modified while transmission or
reception is on-going, the baud rate will not be updated until transmission or
reception of the current character is complete.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DIVINT | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | RESERVED | R | 0h | Reserved |
| 15-0 | DIVINT | R/W | 0h | The integer baud rate divisor: The baud rate divisor is calculated using the formula below: Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) Baud rate divisor must be minimum 1 and maximum 65535. That is, DIVINT=0 does not give a valid baud rate. Similarly, if DIVINT=0xFFFF, any non-zero values in FBRD.DIVFRAC will be illegal. A valid value must be written to this field before the UART can be used for RX or TX operations. |
FBRD is shown in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_FBRD_FIGURE and described in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_FBRD_TABLE.
Return to the Summary Table.
Fractional Baud-Rate Divisor
If this register is modified while trasmission or
reception is on-going, the baudrate will not be updated until transmission or
reception of the current character is complete.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-0h | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DIVFRAC | ||||||||||||||
| R-0h | R/W-0h | ||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-6 | RESERVED | R | 0h | Reserved |
| 5-0 | DIVFRAC | R/W | 0h | Fractional Baud-Rate Divisor: The baud rate divisor is calculated using the formula below: Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) Baud rate divisor must be minimum 1 and maximum 65535. That is, IBRD.DIVINT=0 does not give a valid baud rate. Similarly, if IBRD.DIVINT=0xFFFF, any non-zero values in DIVFRAC will be illegal. A valid value must be written to this field before the UART can be used for RX or TX operations. |
LCRH is shown in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_LCRH_FIGURE and described in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_LCRH_TABLE.
Return to the Summary Table.
Line Control
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SPS | WLEN | FEN | STP2 | EPS | PEN | BRK | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R | 0h | Reserved |
| 7 | SPS | R/W | 0h | UART Stick Parity Select: 0: Stick parity is disabled 1: The parity bit is transmitted and checked as invert of EPS field (i.e. the parity bit is transmitted and checked as 1 when EPS = 0). This bit has no effect when PEN disables parity checking and generation. |
| 6-5 | WLEN | R/W | 0h | UART Word Length: These bits indicate the number of data bits transmitted or received in a frame. 0h = 5 : Word Length 5 bits 1h = 6 : Word Length 6 bits 2h = 7 : Word Length 7 bits 3h = 8 : Word Length 8 bits |
| 4 | FEN | R/W | 0h | UART Enable FIFOs 0h = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers. 1h = Transmit and receive FIFO buffers are enabled (FIFO mode) |
| 3 | STP2 | R/W | 0h | UART Two Stop Bits Select: If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. |
| 2 | EPS | R/W | 0h | UART Even Parity Select 0h = Odd parity: The UART generates or checks for an odd number of 1s in the data and parity bits. 1h = Even parity: The UART generates or checks for an even number of 1s in the data and parity bits. |
| 1 | PEN | R/W | 0h | UART Parity Enable This bit controls generation and checking of parity bit. 0h = Parity is disabled and no parity bit is added to the data frame 1h = Parity checking and generation is enabled. |
| 0 | BRK | R/W | 0h | UART Send Break If this bit is set to 1, a low-level is continually output on the UARTTXD output pin, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. |
CTL is shown in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_CTL_FIGURE and described in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_CTL_TABLE.
Return to the Summary Table.
Control
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CTSEN | RTSEN | RESERVED | RTS | RESERVED | RXE | TXE | |
| R/W-0h | R/W-0h | R-0h | R/W-0h | R-0h | R/W-1h | R/W-1h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LBE | RESERVED | UARTEN | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | RESERVED | R | 0h | Reserved |
| 15 | CTSEN | R/W | 0h | CTS hardware flow control enable 0h = CTS hardware flow control disabled 1h = CTS hardware flow control enabled |
| 14 | RTSEN | R/W | 0h | RTS hardware flow control enable 0h = RTS hardware flow control disabled 1h = RTS hardware flow control enabled |
| 13-12 | RESERVED | R | 0h | Reserved |
| 11 | RTS | R/W | 0h | Request to Send This bit is the complement of the active-low UART RTS output. That is, when the bit is programmed to a 1 then RTS output on the pins is LOW. |
| 10 | RESERVED | R | 0h | Reserved |
| 9 | RXE | R/W | 1h | UART Receive Enable If the UART is disabled in the middle of reception, it completes the current character before stopping. 0h = UART Receive disabled 1h = UART Receive enabled |
| 8 | TXE | R/W | 1h | UART Transmit Enable If the UART is disabled in the middle of transmission, it completes the current character before stopping. 0h = UART Transmit disabled 1h = UART Transmit enabled |
| 7 | LBE | R/W | 0h | UART Loop Back Enable: Enabling the loop-back mode connects the UARTTXD output from the UART to UARTRXD input of the UART. 0h = Loop Back disabled 1h = Loop Back enabled |
| 6-1 | RESERVED | R | 0h | Reserved |
| 0 | UARTEN | R/W | 0h | UART Enable 0h = UART disabled 1h = UART enabled |
IFLS is shown in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_IFLS_FIGURE and described in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_IFLS_TABLE.
Return to the Summary Table.
Interrupt FIFO Level Select
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-0h | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RXSEL | TXSEL | |||||||||||||
| R-0h | R/W-2h | R/W-2h | |||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-6 | RESERVED | R | 0h | Reserved |
| 5-3 | RXSEL | R/W | 2h | Receive interrupt FIFO level select: This field sets the trigger points for the receive interrupt. Values 0b101-0b111 are reserved. 0h = 1_8 : Receive FIFO becomes >= 1/8 full 1h = 2_8 : Receive FIFO becomes >= 1/4 full 2h = 4_8 : Receive FIFO becomes >= 1/2 full 3h = 6_8 : Receive FIFO becomes >= 3/4 full 4h = 7_8 : Receive FIFO becomes >= 7/8 full |
| 2-0 | TXSEL | R/W | 2h | Transmit interrupt FIFO level select: This field sets the trigger points for the transmit interrupt. Values 0b101-0b111 are reserved. 0h = 1_8 : Transmit FIFO becomes <= 1/8 full 1h = 2_8 : Transmit FIFO becomes <= 1/4 full 2h = 4_8 : Transmit FIFO becomes <= 1/2 full 3h = 6_8 : Transmit FIFO becomes <= 3/4 full 4h = 7_8 : Transmit FIFO becomes <= 7/8 full |
IMSC is shown in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_IMSC_FIGURE and described in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_IMSC_TABLE.
Return to the Summary Table.
Interrupt Mask Set/Clear
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | EOTIM | OEIM | BEIM | PEIM | |||
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FEIM | RTIM | TXIM | RXIM | RESERVED | CTSMIM | RESERVED | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-12 | RESERVED | R | 0h | Reserved |
| 11 | EOTIM | R/W | 0h | End of Transmission interrupt mask. A read returns the current mask for UART's EoT interrupt. On a write of 1, the mask of the EoT interrupt is set which means the interrupt state will be reflected in MIS.EOTMIS. A write of 0 clears the mask which means MIS.EOTMIS will not reflect the interrupt. |
| 10 | OEIM | R/W | 0h | Overrun error interrupt mask. A read returns the current mask for UART's overrun error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.OEMIS. A write of 0 clears the mask which means MIS.OEMIS will not reflect the interrupt. |
| 9 | BEIM | R/W | 0h | Break error interrupt mask. A read returns the current mask for UART's break error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.BEMIS. A write of 0 clears the mask which means MIS.BEMIS will not reflect the interrupt. |
| 8 | PEIM | R/W | 0h | Parity error interrupt mask. A read returns the current mask for UART's parity error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.PEMIS. A write of 0 clears the mask which means MIS.PEMIS will not reflect the interrupt. |
| 7 | FEIM | R/W | 0h | Framing error interrupt mask. A read returns the current mask for UART's framing error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.FEMIS. A write of 0 clears the mask which means MIS.FEMIS will not reflect the interrupt. |
| 6 | RTIM | R/W | 0h | Receive timeout interrupt mask. A read returns the
current mask for UART's receive timeout interrupt. On a write of 1,
the mask of the overrun error interrupt is set which means the
interrupt state will be reflected in MIS.RTMIS. A write of 0 clears
the mask which means this bitfield will not reflect the interrupt.
The raw interrupt for receive timeout RIS.RTRIS cannot be set unless the mask is set (RTIM = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from MIS.RTMIS and RIS.RTRIS. |
| 5 | TXIM | R/W | 0h | Transmit interrupt mask. A read returns the current mask for UART's transmit interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS will not reflect the interrupt. |
| 4 | RXIM | R/W | 0h | Receive interrupt mask. A read returns the current mask for UART's receive interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 clears the mask which means MIS.RXMIS will not reflect the interrupt. |
| 3-2 | RESERVED | R | 0h | Reserved |
| 1 | CTSMIM | R/W | 0h | Clear to Send (CTS) modem interrupt mask. A read returns the current mask for UART's clear to send interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.CTSMMIS. A write of 0 clears the mask which means MIS.CTSMMIS will not reflect the interrupt. |
| 0 | RESERVED | R | 0h | Reserved |
RIS is shown in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_RIS_FIGURE and described in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_RIS_TABLE.
Return to the Summary Table.
Raw Interrupt Status
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | EOTRIS | OERIS | BERIS | PERIS | |||
| R-0h | R-0h | R-0h | R-0h | R-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FERIS | RTRIS | TXRIS | RXRIS | RESERVED | CTSRMIS | RESERVED | |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-X | R-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-12 | RESERVED | R | 0h | Reserved |
| 11 | EOTRIS | R | 0h | End of Transmission interrupt status: This field returns the raw interrupt state of UART's end of transmission interrupt. End of transmission flag is set when all the Transmit data in the FIFO and on the TX Line is tranmitted. |
| 10 | OERIS | R | 0h | Overrun error interrupt status: This field returns the raw interrupt state of UART's overrun error interrupt. Overrun error occurs if data is received and the receive FIFO is full. |
| 9 | BERIS | R | 0h | Break error interrupt status: This field returns the raw interrupt state of UART's break error interrupt. Break error is set when a break condition is detected, indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). |
| 8 | PERIS | R | 0h | Parity error interrupt status: This field returns the raw interrupt state of UART's parity error interrupt. Parity error is set if the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select. |
| 7 | FERIS | R | 0h | Framing error interrupt status: This field returns the raw interrupt state of UART's framing error interrupt. Framing error is set if the received character does not have a valid stop bit (a valid stop bit is 1). |
| 6 | RTRIS | R | 0h | Receive timeout interrupt status: This field returns the raw interrupt state of UART's receive timeout interrupt. The receive timeout interrupt is asserted when the receive FIFO is not empty, and no more data is received during a 32-bit period. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data, or when a 1 is written to ICR.RTIC. The raw interrupt for receive timeout cannot be set unless the mask is set (IMSC.RTIM = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from MIS.RTMIS and RTRIS. |
| 5 | TXRIS | R | 0h | Transmit interrupt status: This field returns the raw interrupt state of UART's transmit interrupt. When FIFOs are enabled (LCRH.FEN = 1), the transmit interrupt is asserted if the number of bytes in transmit FIFO is equal to or lower than the programmed trigger level (IFLS.TXSEL). The transmit interrupt is cleared by writing data to the transmit FIFO until it becomes greater than the trigger level, or by clearing the interrupt through ICR.TXIC. When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one location, the transmit interrupt is asserted if there is no data present in the transmitters single location. It is cleared by performing a single write to the transmit FIFO, or by clearing the interrupt through ICR.TXIC. |
| 4 | RXRIS | R | 0h | Receive interrupt status: This field returns the raw interrupt state of UART's receive interrupt. When FIFOs are enabled (LCRH.FEN = 1), the receive interrupt is asserted if the receive FIFO reaches the programmed trigger level (IFLS.RXSEL). The receive interrupt is cleared by reading data from the receive FIFO until it becomes less than the trigger level, or by clearing the interrupt through ICR.RXIC. When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one location, the receive interrupt is asserted if data is received thereby filling the location. The receive interrupt is cleared by performing a single read of the receive FIFO, or by clearing the interrupt through ICR.RXIC. |
| 3-2 | RESERVED | R | 0h | Reserved |
| 1 | CTSRMIS | R | X | Clear to Send (CTS) modem interrupt status: This field returns the raw interrupt state of UART's clear to send interrupt. |
| 0 | RESERVED | R | 0h | Reserved |
MIS is shown in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_MIS_FIGURE and described in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_MIS_TABLE.
Return to the Summary Table.
Masked Interrupt Status
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | EOTMIS | OEMIS | BEMIS | PEMIS | |||
| R-0h | R-0h | R-0h | R-0h | R-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FEMIS | RTMIS | TXMIS | RXMIS | RESERVED | CTSMMIS | RESERVED | |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-12 | RESERVED | R | 0h | Reserved |
| 11 | EOTMIS | R | 0h | End of Transmission interrupt status: This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state RIS.EOTRIS and the mask setting IMSC.EOTIM. |
| 10 | OEMIS | R | 0h | Overrun error masked interrupt status: This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state RIS.OERIS and the mask setting IMSC.OEIM. |
| 9 | BEMIS | R | 0h | Break error masked interrupt status: This field returns the masked interrupt state of the break error interrupt which is the AND product of raw interrupt state RIS.BERIS and the mask setting IMSC.BEIM. |
| 8 | PEMIS | R | 0h | Parity error masked interrupt status: This field returns the masked interrupt state of the parity error interrupt which is the AND product of raw interrupt state RIS.PERIS and the mask setting IMSC.PEIM. |
| 7 | FEMIS | R | 0h | Framing error masked interrupt status: Returns the masked interrupt state of the framing error interrupt which is the AND product of raw interrupt state RIS.FERIS and the mask setting IMSC.FEIM. |
| 6 | RTMIS | R | 0h | Receive timeout masked interrupt status: Returns the masked interrupt state of the receive timeout interrupt. The raw interrupt for receive timeout cannot be set unless the mask is set (IMSC.RTIM = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from RTMIS and RIS.RTRIS. |
| 5 | TXMIS | R | 0h | Transmit masked interrupt status: This field returns the masked interrupt state of the transmit interrupt which is the AND product of raw interrupt state RIS.TXRIS and the mask setting IMSC.TXIM. |
| 4 | RXMIS | R | 0h | Receive masked interrupt status: This field returns the masked interrupt state of the receive interrupt which is the AND product of raw interrupt state RIS.RXRIS and the mask setting IMSC.RXIM. |
| 3-2 | RESERVED | R | 0h | Reserved |
| 1 | CTSMMIS | R | 0h | Clear to Send (CTS) modem masked interrupt status: This field returns the masked interrupt state of the clear to send interrupt which is the AND product of raw interrupt state RIS.CTSRMIS and the mask setting IMSC.CTSMIM. |
| 0 | RESERVED | R | 0h | Reserved |
ICR is shown in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_ICR_FIGURE and described in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_ICR_TABLE.
Return to the Summary Table.
Interrupt Clear
On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | EOTIC | OEIC | BEIC | PEIC | |||
| R-0h | W-X | W-X | W-X | W-X | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FEIC | RTIC | TXIC | RXIC | RESERVED | CTSMIC | RESERVED | |
| W-X | W-X | W-X | W-X | W-X | W-X | W-X | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-12 | RESERVED | R | 0h | Reserved |
| 11 | EOTIC | W | X | End of Transmission interrupt clear: Writing 1 to this field clears the overrun error interrupt (RIS.EOTRIS). Writing 0 has no effect. |
| 10 | OEIC | W | X | Overrun error interrupt clear: Writing 1 to this field clears the overrun error interrupt (RIS.OERIS). Writing 0 has no effect. |
| 9 | BEIC | W | X | Break error interrupt clear: Writing 1 to this field clears the break error interrupt (RIS.BERIS). Writing 0 has no effect. |
| 8 | PEIC | W | X | Parity error interrupt clear: Writing 1 to this field clears the parity error interrupt (RIS.PERIS). Writing 0 has no effect. |
| 7 | FEIC | W | X | Framing error interrupt clear: Writing 1 to this field clears the framing error interrupt (RIS.FERIS). Writing 0 has no effect. |
| 6 | RTIC | W | X | Receive timeout interrupt clear: Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS). Writing 0 has no effect. |
| 5 | TXIC | W | X | Transmit interrupt clear: Writing 1 to this field clears the transmit interrupt (RIS.TXRIS). Writing 0 has no effect. |
| 4 | RXIC | W | X | Receive interrupt clear: Writing 1 to this field clears the receive interrupt (RIS.RXRIS). Writing 0 has no effect. |
| 3-2 | RESERVED | W | X | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Write 0 |
| 1 | CTSMIC | W | X | Clear to Send (CTS) modem interrupt clear: Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS). Writing 0 has no effect. |
| 0 | RESERVED | W | X | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Write 0. |
DMACTL is shown in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_DMACTL_FIGURE and described in #UART_PL011_R1P5_UART_PL011_R1P5_MAP1_UART_PL011_R1P5_ALL_DMACTL_TABLE.
Return to the Summary Table.
DMA Control
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DMAONERR | TXDMAE | RXDMAE | ||||
| R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-3 | RESERVED | R | 0h | Reserved |
| 2 | DMAONERR | R/W | 0h | DMA on error. If this bit is set to 1, the DMA receive request outputs (for single and burst requests) are disabled when the UART error interrupt is asserted (more specifically if any of the error interrupts RIS.PERIS, RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted). |
| 1 | TXDMAE | R/W | 0h | Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. |
| 0 | RXDMAE | R/W | 0h | Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. |