SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The SSI peripheral provides an interface to the μDMA controller with separate channels for transmit and receive. The SSI DMA Control register (SSI:DMACR) allows the μDMA to operate the SSI. When μDMA operation is enabled, the SSI asserts a μDMA request on the receive or transmit channel when the associated FIFO can transfer data. For the receive channel, a single transfer request is asserted whenever any data is in the RX FIFO. Whenever data in the RX FIFO is four or more items, a burst transfer request is asserted. For the transmit channel, a single transfer request is asserted whenever at least one empty location is in the TX FIFO. Whenever the TX FIFO has four or more empty slots, the burst request is asserted. The μDMA controller handles the single and burst μDMA transfer requests automatically depending on how the μDMA channel is configured.
To enable μDMA operation for the receive channel, set the SSI:DMACR RXDMAE register bit. To enable μDMA operation for the transmit channel, set the SSI:MAC RTXDMAE register bit. If the μDMA is enabled and appropriate bits are cleared in the DMA Done Mask register (UDMA:DONEMASK) the μDMA controller triggers an interrupt when a transfer completes. The interrupt occurs on the SSI interrupt vector. If interrupts are used for SSI operation and the μDMA is enabled, the SSI interrupt handler must be designed to handle the μDMA completion interrupt. The status of TX and RX DMA done interrupts can be read from the Channel Request Done register (UDMA:REQDONE). For clearing the TX and RX DMA done interrupts, the corresponding bits in the UDMA:REQDONE register must be 1.
For more details about programming the μDMA controller, see Section 15.