SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
7.9 Profiler Register
This register can be used to extract runtime information from the chip with no intrusion to the code execution. This register resides in the TEST TAP (the profiler register IR number is 0x06). For more details, see Table 7-24.
Figure 7-12 Profiler Register
Table 7-24 Profiler Register Fields
| Bits | Width | Description | |
|---|---|---|---|
| 81–80 | 2 | AON_PMCTL:PWRSTAT.SW | |
| 79 | 1 | AUX_SYSIF:ADCCLKCTL.REQ | |
| 78 | 1 | AUX_SYSIF:TDCCLKCTL.REQ | |
| 77 | 1 | AUX_ANAIF:DACSMPLCTL.EN | |
| 76–74 | 3 | AUX_SYSIF:SWPWRPROF.STAT | |
| 73–72 | 2 | AUX_SYSIF:OPMODESTAT.STATE | |
| 71 | 1 | AUX_SCE:CTL.RUN and not AUX_SCE:CPUSTAT.SLEEP | |
| 70 | 1 | Clock state for SYSBUS(1): 0: Clock is not running. 1: Clock is running. | |
| 69 | 1 | Clock state for FLASH(1): 0: Clock is not running. 1: Clock is running. | |
| 68 | 1 | Clock state for RFCORE(1): 0: Clock is not running. 1: Clock is running. | |
| 67 | 1 | Clock state for GPIO(1): 0: Clock is not running. 1: Clock is running. | |
| 66 | 1 | Clock state for GPTM0(1): 0: Clock is not running. 1: Clock is running. | |
| 65 | 1 | Clock state for GPTM1(1): 0: Clock is not running. 1: Clock is running. | |
| 64 | 1 | Clock state for GPTM2(1): 0: Clock is not running. 1: Clock is running. | |
| 63 | 1 | Clock state for GPTM3(1): 0: Clock is not running. 1: Clock is running. | |
| 62 | 1 | Clock state for I2C(1): 0: Clock is not running. 1: Clock is running. | |
| 61 | 1 | Clock state for I2S(1): 0: Clock is not running. 1: Clock is running. | |
| 60 | 1 | Clock state for UDMA(1): 0: Clock is not running. 1: Clock is running. | |
| 59 | 1 | Clock state for TRNG(1): 0: Clock is not running. 1: Clock is running. | |
| 58 | 1 | Clock state for CRYPTO(1): 0: Clock is not running. 1: Clock is running. | |
| 57 | 1 | Clock state for PKA(1): 0: Clock is not running. 1: Clock is running. | |
| 56 | 1 | Clock state for SSI0(1): 0: Clock is not running. 1: Clock is running. | |
| 55 | 1 | Clock state for SSI1(1): 0: Clock is not running. 1: Clock is running. | |
| 54 | 1 | Clock state for UART0(1): 0: Clock is not running. 1: Clock is running. | |
| 53 | 1 | Clock state for UART1(1): 0: Clock is not running. 1: Clock is running. | |
| 52 | 1 | Sleep request from CPU | |
| 51 | 1 | Deep sleep request from CPU qualified by WIC | |
| 50 | 1 | Reserved | |
| 49 | 1 | CPU PD status: 0: Power domain is off. 1: Power domain is on. | |
| 48 | 1 | SERIAL PD status: 0: Power domain is off. 1: Power domain is on. | |
| 47 | 1 | PERIPH PD status: 0: Power domain is off. 1: Power domain is on. | |
| 46 | 1 | RFCORE PD status: 0: Power domain is off. 1: Power domain is on. | |
| 45 | 1 | VIMS PD status: 0: Power domain is off. 1: Power domain is on. | |
| 44 | 1 | MCU power state: 0: STANDBY 1: ACTIVE | |
| 43 | 1 | DDI_0_OSC:STAT0.XOSC_HF_EN | |
| 42 | 1 | DDI_0_OSC:STAT0.SCLK_HF_SRC | |
| 41–40 | 2 | DDI_0_OSC:STAT0.SCLK_LF_SRC | |
| 39–36 | 4 | RF_CORE_STATE: | |
| b0000 NA b0001 IDLE b0010 RFACTIVE b0110 RXWAIT b1110 RXPACKET b1010 TX | No Information yet available or RF Core powered off. The RF Core is powered but idle; no RF. The RF Synthesizer is active. The RF Core is waiting for sync. The RF Core is receiving a packet. The RF Core is transmitting a packet | ||
| Others Reserved | |||
| 35–28 | 8 | PRCM:PWRPROFSTAT | |
| 27 | 1 | Error in values of compressed program counter: 1: The value returned in bits 26–6 cannot be trusted. 0: The value returned in bits 26–6 can be trusted. | |
| 26–6 | 21 | Compressed program counter (removing 11 of the 32-bit program counter which are expected to be 0) Active bits of the program counter {PC[29:28],PC[24], PC[18:1]} | |
| 5–0 | 6 | Indicates the interrupt number of the current execution context in the CPU | |
(1) This field may be invalid if the MCU power state is in STANDBY.