SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
Each secondary TAP is assigned a number. The TAP numbering is linear and starts with 0. The number assigned to a secondary TAP corresponds to its location within the secondary control and status registers in ICEPick. The first selected TAP is the TAP with the lowest number, while the last selected TAP is the TAP with the highest number. The ICEPick module has a firewall for unauthorized access of slave TAPs. Table 7-5 lists the available TAPs, their corresponding order, and the availability of these TAPs for end user. The open TAPs can be locked by writing to the corresponding field in the customer configuration area.
| Number | Test TAP Name | Description | Availability for End User |
|---|---|---|---|
| Test Banks | |||
| 0 | TEST | DFT functionalities and profiler | See (1) |
| 1 | PBIST1.0 | RAM BIST controller interface | Locked |
| 2 | PBIST2.0 | ROM BIST controller interface | Locked |
| 3 | eFuse | eFuse interface for SRAM repair | Locked |
| 4 | Reserved | Reserved | Reserved |
| 5 | AON WUC | VD override control/status | See (2) |
| Debug Banks | |||
| 0 | CM4F | DAP for Cortex-M4F debug | See (2)(3) |