SWCU192 November   2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

 

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    9.     402
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  14.   404
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    4.     448
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    5.     454
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  16.   456
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    3.     459
      1.      460
      2.      461
        1.       462
        2.       463
        3.       464
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        5.       466
      3.      467
      4.      468
    4.     469
      1.      470
      2.      471
      3.      472
      4.      473
      5.      474
    5.     475
      1.      476
  17.   477
    1.     478
    2.     479
      1.      480
      2.      481
      3.      482
        1.       483
      4.      484
    3.     485
      1.      486
      2.      487
      3.      488
    4.     489
      1.      490
  18.   491
    1.     492
    2.     493
    3.     494
    4.     495
      1.      496
  19.   497
    1.     498
    2.     499
    3.     500
    4.     501
    5.     502
      1.      503
      2.      504
      3.      505
    6.     506
      1.      507
        1.       508
        2.       509
        3.       510
          1.        511
          2.        512
    7.     513
      1.      514
  20.   515
    1.     516
      1.      517
    2.     518
      1.      519
        1.       520
      2.      521
        1.       522
        2.       523
      3.      524
      4.      525
    3.     526
      1.      527
        1.       528
        2.       529
        3.       530
        4.       531
      2.      532
        1.       533
          1.        534
        2.       535
          1.        536
          2.        537
        3.       538
          1.        539
        4.       540
          1.        541
          2.        542
          3.        543
        5.       544
        6.       545
        7.       546
        8.       547
        9.       548
        10.       549
    4.     550
      1.      551
        1.       552
      2.      553
        1.       554
        2.       555
          1.        556
          2.        557
          3.        558
          4.        559
          5.        560
      3.      561
        1.       562
        2.       563
        3.       564
      4.      565
        1.       566
        2.       567
          1.        568
          2.        569
          3.        570
      5.      571
        1.       572
        2.       573
          1.        574
          2.        575
          3.        576
          4.        577
            1.         578
            2.         579
          5.        580
          6.        581
        3.       582
          1.        583
          2.        584
          3.        585
            1.         586
            2.         587
            3.         588
            4.         589
          4.        590
      6.      591
        1.       592
        2.       593
      7.      594
        1.       595
        2.       596
          1.        597
          2.        598
          3.        599
          4.        600
          5.        601
            1.         602
              1.          603
            2.         604
              1.          605
            3.         606
              1.          607
          6.        608
    5.     609
      1.      610
        1.       611
        2.       612
      2.      613
        1.       614
        2.       615
          1.        616
          2.        617
          3.        618
          4.        619
          5.        620
          6.        621
          7.        622
          8.        623
      3.      624
        1.       625
        2.       626
          1.        627
          2.        628
          3.        629
          4.        630
      4.      631
        1.       632
        2.       633
          1.        634
          2.        635
          3.        636
            1.         637
            2.         638
      5.      639
        1.       640
        2.       641
          1.        642
          2.        643
          3.        644
            1.         645
            2.         646
            3.         647
          4.        648
            1.         649
            2.         650
            3.         651
            4.         652
          5.        653
          6.        654
      6.      655
        1.       656
        2.       657
          1.        658
          2.        659
          3.        660
          4.        661
          5.        662
    6.     663
      1.      664
        1.       665
        2.       666
          1.        667
            1.         668
            2.         669
      2.      670
      3.      671
      4.      672
      5.      673
      6.      674
      7.      675
    7.     676
    8.     677
      1.      678
      2.      679
      3.      680
      4.      681
      5.      682
      6.      683
      7.      684
      8.      685
      9.      686
      10.      687
      11.      688
      12.      689
  21.   690
    1.     691
    2.     692
    3.     693
      1.      694
  22.   695
    1.     696
    2.     697
    3.     698
    4.     699
      1.      700
      2.      701
      3.      702
      4.      703
        1.       704
        2.       705
          1.        706
          2.        707
      5.      708
      6.      709
      7.      710
    5.     711
    6.     712
    7.     713
      1.      714
  23.   715
    1.     716
    2.     717
    3.     718
    4.     719
      1.      720
      2.      721
        1.       722
        2.       723
      3.      724
      4.      725
        1.       726
        2.       727
          1.        728
          2.        729
        3.       730
        4.       731
        5.       732
        6.       733
        7.       734
    5.     735
    6.     736
    7.     737
      1.      738
  24.   739
    1.     740
    2.     741
    3.     742
      1.      743
        1.       744
        2.       745
        3.       746
        4.       747
        5.       748
      2.      749
        1.       750
      3.      751
        1.       752
        2.       753
      4.      754
      5.      755
        1.       756
        2.       757
    4.     758
    5.     759
      1.      760
  25.   761
    1.     762
    2.     763
    3.     764
    4.     765
      1.      766
        1.       767
      2.      768
      3.      769
      4.      770
        1.       771
      5.      772
        1.       773
      6.      774
        1.       775
      7.      776
        1.       777
      8.      778
        1.       779
        2.       780
    5.     781
      1.      782
      2.      783
      3.      784
      4.      785
        1.       786
        2.       787
        3.       788
    6.     789
      1.      790
      2.      791
      3.      792
      4.      793
    7.     794
    8.     795
      1.      796
      2.      797
    9.     798
      1.      799
  26.   800
    1.     801
      1.      802
    2.     803
      1.      804
      2.      805
      3.      806
        1.       807
        2.       808
        3.       809
      4.      810
        1.       811
        2.       812
        3.       813
    3.     814
      1.      815
      2.      816
        1.       817
        2.       818
        3.       819
        4.       820
        5.       821
          1.        822
          2.        823
          3.        824
        6.       825
          1.        826
        7.       827
          1.        828
          2.        829
          3.        830
          4.        831
        8.       832
      3.      833
        1.       834
          1.        835
          2.        836
          3.        837
          4.        838
          5.        839
          6.        840
          7.        841
          8.        842
          9.        843
          10.        844
          11.        845
          12.        846
          13.        847
          14.        848
        2.       849
          1.        850
          2.        851
          3.        852
          4.        853
          5.        854
          6.        855
          7.        856
          8.        857
          9.        858
          10.        859
          11.        860
          12.        861
          13.        862
          14.        863
          15.        864
          16.        865
          17.        866
          18.        867
          19.        868
          20.        869
      4.      870
        1.       871
        2.       872
        3.       873
        4.       874
        5.       875
    4.     876
      1.      877
        1.       878
        2.       879
        3.       880
        4.       881
        5.       882
      2.      883
        1.       884
        2.       885
    5.     886
      1.      887
        1.       888
        2.       889
        3.       890
        4.       891
      2.      892
      3.      893
        1.       894
        2.       895
      4.      896
        1.       897
          1.        898
            1.         899
            2.         900
          2.        901
          3.        902
          4.        903
          5.        904
        2.       905
        3.       906
        4.       907
        5.       908
        6.       909
      5.      910
        1.       911
        2.       912
        3.       913
        4.       914
        5.       915
        6.       916
    6.     917
      1.      918
        1.       919
          1.        920
        2.       921
        3.       922
        4.       923
      2.      924
    7.     925
      1.      926
      2.      927
    8.     928
      1.      929
      2.      930
      3.      931
      4.      932
      5.      933
      6.      934
      7.      935
      8.      936
        1.       937
        2.       938
        3.       939
        4.       940
      9.      941
        1.       942
        2.       943
        3.       944
      10.      945
        1.       946
        2.       947
        3.       948
        4.       949
        5.       950
      11.      951
        1.       952
        2.       953
        3.       954
        4.       955
        5.       956
      12.      957
      13.      958
      14.      959
      15.      960
      16.      961
      17.      962
    9.     963
      1.      964
    10.     965
      1.      966
      2.      967
        1.       968
          1.        969
        2.       970
        3.       971
      3.      972
      4.      973
        1.       974
        2.       975
      5.      976
        1.       977
        2.       978
          1.        979
        3.       980
          1.        981
          2.        982
        4.       983
          1.        984
          2.        985
        5.       986
          1.        987
          2.        988
          3.        989
      6.      990
        1.       991
        2.       992
    11.     993
      1.      994
      2.      995
      3.      996
  27.   997

19.7.1 TRNG Registers

#TRNG_TRNG_MAP1_TABLE_1 lists the memory-mapped registers for the TRNG registers. All register offset addresses not listed in #TRNG_TRNG_MAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 19-5 TRNG Registers
Offset Acronym Register Name Section
0h OUT0 Random Number Lower Word Readout Value #TRNG_TRNG_MAP1_TRNG_ALL_OUT0
4h OUT1 Random Number Upper Word Readout Value #TRNG_TRNG_MAP1_TRNG_ALL_OUT1
8h IRQFLAGSTAT Interrupt Status #TRNG_TRNG_MAP1_TRNG_ALL_IRQFLAGSTAT
Ch IRQFLAGMASK Interrupt Mask #TRNG_TRNG_MAP1_TRNG_ALL_IRQFLAGMASK
10h IRQFLAGCLR Interrupt Flag Clear #TRNG_TRNG_MAP1_TRNG_ALL_IRQFLAGCLR
14h CTL Control #TRNG_TRNG_MAP1_TRNG_ALL_CTL
18h CFG0 Configuration 0 #TRNG_TRNG_MAP1_TRNG_ALL_CFG0
1Ch ALARMCNT Alarm Control #TRNG_TRNG_MAP1_TRNG_ALL_ALARMCNT
20h FROEN FRO Enable #TRNG_TRNG_MAP1_TRNG_ALL_FROEN
24h FRODETUNE FRO De-tune Bit #TRNG_TRNG_MAP1_TRNG_ALL_FRODETUNE
28h ALARMMASK Alarm Event #TRNG_TRNG_MAP1_TRNG_ALL_ALARMMASK
2Ch ALARMSTOP Alarm Shutdown #TRNG_TRNG_MAP1_TRNG_ALL_ALARMSTOP
30h LFSR0 LFSR Readout Value #TRNG_TRNG_MAP1_TRNG_ALL_LFSR0
34h LFSR1 LFSR Readout Value #TRNG_TRNG_MAP1_TRNG_ALL_LFSR1
38h LFSR2 LFSR Readout Value #TRNG_TRNG_MAP1_TRNG_ALL_LFSR2
78h HWOPT TRNG Engine Options Information #TRNG_TRNG_MAP1_TRNG_ALL_HWOPT
7Ch HWVER0 HW Version 0 #TRNG_TRNG_MAP1_TRNG_ALL_HWVER0
1FD8h IRQSTATMASK Interrupt Status After Masking #TRNG_TRNG_MAP1_TRNG_ALL_IRQSTATMASK
1FE0h HWVER1 HW Version 1 #TRNG_TRNG_MAP1_TRNG_ALL_HWVER1
1FECh IRQSET Interrupt Set #TRNG_TRNG_MAP1_TRNG_ALL_IRQSET
1FF0h SWRESET SW Reset Control #TRNG_TRNG_MAP1_TRNG_ALL_SWRESET
1FF8h IRQSTAT Interrupt Status #TRNG_TRNG_MAP1_TRNG_ALL_IRQSTAT

Complex bit access types are encoded to fit into small table cells. #TRNG_TRNG_MAP1_LEGEND shows the codes that are used for access types in this section.

Table 19-6 TRNG Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

19.7.1.1 OUT0 Register (Offset = 0h) [Reset = 00000000h]

OUT0 is shown in #TRNG_TRNG_MAP1_TRNG_ALL_OUT0_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_OUT0_TABLE.

Return to the Summary Table.

Random Number Lower Word Readout Value

Figure 19-4 OUT0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VALUE_31_0
R-0h
Table 19-7 OUT0 Register Field Descriptions
Bit Field Type Reset Description
31-0 VALUE_31_0 R 0h LSW of 64- bit random value. New value ready when IRQFLAGSTAT.RDY = 1.

19.7.1.2 OUT1 Register (Offset = 4h) [Reset = 00000000h]

OUT1 is shown in #TRNG_TRNG_MAP1_TRNG_ALL_OUT1_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_OUT1_TABLE.

Return to the Summary Table.

Random Number Upper Word Readout Value

Figure 19-5 OUT1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VALUE_63_32
R-0h
Table 19-8 OUT1 Register Field Descriptions
Bit Field Type Reset Description
31-0 VALUE_63_32 R 0h MSW of 64-bit random value. New value ready when IRQFLAGSTAT.RDY = 1.

19.7.1.3 IRQFLAGSTAT Register (Offset = 8h) [Reset = 00000000h]

IRQFLAGSTAT is shown in #TRNG_TRNG_MAP1_TRNG_ALL_IRQFLAGSTAT_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_IRQFLAGSTAT_TABLE.

Return to the Summary Table.

Interrupt Status

Figure 19-6 IRQFLAGSTAT Register
31 30 29 28 27 26 25 24
NEED_CLOCK RESERVED
R-0h R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED SHUTDOWN_OVF RDY
R-0h R-0h R-0h
Table 19-9 IRQFLAGSTAT Register Field Descriptions
Bit Field Type Reset Description
31 NEED_CLOCK R 0h 1: Indicates that the TRNG is busy generating entropy or is in one of its test modes - clocks may not be turned off and the power supply voltage must be kept stable.
0: TRNG is idle and can be shut down
30-2 RESERVED R 0h Reserved
1 SHUTDOWN_OVF R 0h 1: The number of FROs shut down (i.e. the number of '1' bits in the ALARMSTOP register) has exceeded the threshold set by ALARMCNT.SHUTDOWN_THR
Writing '1' to IRQFLAGCLR.SHUTDOWN_OVF clears this bit to '0' again.
0 RDY R 0h 1: Data are available in OUT0 and OUT1.
Acknowledging this state by writing '1' to IRQFLAGCLR.RDY clears this bit to '0'.
If a new number is already available in the internal register of the TRNG, the number is directly clocked into the result register. In this case the status bit is asserted again, after one clock cycle.

19.7.1.4 IRQFLAGMASK Register (Offset = Ch) [Reset = 00000000h]

IRQFLAGMASK is shown in #TRNG_TRNG_MAP1_TRNG_ALL_IRQFLAGMASK_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_IRQFLAGMASK_TABLE.

Return to the Summary Table.

Interrupt Mask

Figure 19-7 IRQFLAGMASK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED SHUTDOWN_OVF RDY
R-0h R/W-0h R/W-0h
Table 19-10 IRQFLAGMASK Register Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R 0h Reserved
1 SHUTDOWN_OVF R/W 0h 1: Allow IRQFLAGSTAT.SHUTDOWN_OVF to activate the interrupt from this module.
0 RDY R/W 0h 1: Allow IRQFLAGSTAT.RDY to activate the interrupt from this module.

19.7.1.5 IRQFLAGCLR Register (Offset = 10h) [Reset = 00000000h]

IRQFLAGCLR is shown in #TRNG_TRNG_MAP1_TRNG_ALL_IRQFLAGCLR_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_IRQFLAGCLR_TABLE.

Return to the Summary Table.

Interrupt Flag Clear

Figure 19-8 IRQFLAGCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED SHUTDOWN_OVF RDY
R-0h W-0h W-0h
Table 19-11 IRQFLAGCLR Register Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R 0h Reserved
1 SHUTDOWN_OVF W 0h 1: Clear IRQFLAGSTAT.SHUTDOWN_OVF.
0 RDY W 0h 1: Clear IRQFLAGSTAT.RDY.

19.7.1.6 CTL Register (Offset = 14h) [Reset = 00000000h]

CTL is shown in #TRNG_TRNG_MAP1_TRNG_ALL_CTL_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_CTL_TABLE.

Return to the Summary Table.

Control

Figure 19-9 CTL Register
31 30 29 28 27 26 25 24
STARTUP_CYCLES
R/W-0h
23 22 21 20 19 18 17 16
STARTUP_CYCLES
R/W-0h
15 14 13 12 11 10 9 8
RESERVED TRNG_EN RESERVED
R-0h R/W-0h R-0h
7 6 5 4 3 2 1 0
RESERVED NO_LFSR_FB TEST_MODE RESERVED
R-0h R/W-0h R/W-0h R-0h
Table 19-12 CTL Register Field Descriptions
Bit Field Type Reset Description
31-16 STARTUP_CYCLES R/W 0h This field determines the number of samples (between 28 and 224) taken to gather entropy from the FROs during startup. If the written value of this field is zero, the number of samples is 224, otherwise the number of samples equals the written value times 28.
0x0000: 224 samples
0x0001: 1*28 samples
0x0002: 2*28 samples
0x0003: 3*28 samples
...
0x8000: 32768*28 samples
0xC000: 49152*28 samples
...
0xFFFF: 65535*28 samples
This field can only be modified while TRNG_EN is 0. If 1 an update will be ignored.
15-11 RESERVED R 0h Reserved
10 TRNG_EN R/W 0h 0: Forces all TRNG logic back into the idle state immediately.
1: Starts TRNG, gathering entropy from the FROs for the number of samples determined by STARTUP_CYCLES.
9-3 RESERVED R 0h Reserved
2 NO_LFSR_FB R/W 0h 1: Remove XNOR feedback from the main LFSR, converting it into a normal shift register for the XOR-ed outputs of the FROs (shifting data in on the LSB side). A '1' also forces the LFSR to sample continuously.
This bit can only be set to '1' when TEST_MODE is also set to '1' and should not be used for other than test purposes
1 TEST_MODE R/W 0h 1: Enables access to the TESTCNT and LFSR0/LFSR1/LFSR2 registers (the latter are automatically cleared before enabling access) and keeps IRQFLAGSTAT.NEED_CLOCK at '1'.
This bit shall not be used unless you need to change the LFSR seed prior to creating a new random value. All other testing is done external to register control.
0 RESERVED R 0h Reserved

19.7.1.7 CFG0 Register (Offset = 18h) [Reset = 00000000h]

CFG0 is shown in #TRNG_TRNG_MAP1_TRNG_ALL_CFG0_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_CFG0_TABLE.

Return to the Summary Table.

Configuration 0

Figure 19-10 CFG0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_REFILL_CYCLES
R/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SMPL_DIV MIN_REFILL_CYCLES
R-0h R/W-0h R/W-0h
Table 19-13 CFG0 Register Field Descriptions
Bit Field Type Reset Description
31-16 MAX_REFILL_CYCLES R/W 0h This field determines the maximum number of samples (between 28 and 224) taken to re-generate entropy from the FROs after reading out a 64 bits random number. If the written value of this field is zero, the number of samples is 224, otherwise the number of samples equals the written value times 28.
0x0000: 224 samples
0x0001: 1*28 samples
0x0002: 2*28 samples
0x0003: 3*28 samples
...
0x8000: 32768*28 samples
0xC000: 49152*28 samples
...
0xFFFF: 65535*28 samples
This field can only be modified while CTL.TRNG_EN is 0.
15-12 RESERVED R 0h Reserved
11-8 SMPL_DIV R/W 0h This field directly controls the number of clock cycles between samples taken from the FROs. Default value 0 indicates that samples are taken every clock cycle,
maximum value 0xF takes one sample every 16 clock cycles.
This field must be set to a value such that the slowest FRO (even under worst-case
conditions) has a cycle time less than twice the sample period.
This field can only be modified while CTL.TRNG_EN is '0'.
7-0 MIN_REFILL_CYCLES R/W 0h This field determines the minimum number of samples (between 26 and 214) taken to re-generate entropy from the FROs after reading out a 64 bits random number. If the value of this field is zero, the number of samples is fixed to the value determined by the MAX_REFILL_CYCLES field, otherwise the minimum number of samples equals the written value times 64 (which can be up to 214). To ensure same entropy in all generated random numbers the value 0 should be used. Then MAX_REFILL_CYCLES controls the minimum refill interval. The number of samples defined here cannot be higher than the number defined by the 'max_refill_cycles' field (i.e. that field takes precedence). No random value will be created if min refill > max refill.
This field can only be modified while CTL.TRNG_EN = 0.
0x00: Minimum samples = MAX_REFILL_CYCLES (all numbers have same entropy)
0x01: 1*26 samples
0x02: 2*26 samples
...
0xFF: 255*26 samples

19.7.1.8 ALARMCNT Register (Offset = 1Ch) [Reset = 000000FFh]

ALARMCNT is shown in #TRNG_TRNG_MAP1_TRNG_ALL_ALARMCNT_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_ALARMCNT_TABLE.

Return to the Summary Table.

Alarm Control

Figure 19-11 ALARMCNT Register
31 30 29 28 27 26 25 24
RESERVED SHUTDOWN_CNT
R-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED SHUTDOWN_THR
R-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
ALARM_THR
R/W-FFh
Table 19-14 ALARMCNT Register Field Descriptions
Bit Field Type Reset Description
31-30 RESERVED R 0h Reserved
29-24 SHUTDOWN_CNT R/W 0h Read-only, indicates the number of '1' bits in ALARMSTOP register.
The maximum value equals the number of FROs.
23-21 RESERVED R 0h Reserved
20-16 SHUTDOWN_THR R/W 0h Threshold setting for generating IRQFLAGSTAT.SHUTDOWN_OVF interrupt. The interrupt is triggered when SHUTDOWN_CNT value exceeds this bit field.
15-8 RESERVED R 0h Reserved
7-0 ALARM_THR R/W FFh Alarm detection threshold for the repeating pattern detectors on each FRO. An FRO 'alarm event' is declared when a repeating pattern (of up to four samples length) is detected continuously for the number of samples defined by this field's value. Reset value 0xFF should keep the number of 'alarm events' to a manageable level.

19.7.1.9 FROEN Register (Offset = 20h) [Reset = 00FFFFFFh]

FROEN is shown in #TRNG_TRNG_MAP1_TRNG_ALL_FROEN_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_FROEN_TABLE.

Return to the Summary Table.

FRO Enable

Figure 19-12 FROEN Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED FRO_MASK
R-0h R/W-00FFFFFFh
Table 19-15 FROEN Register Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h Reserved
23-0 FRO_MASK R/W 00FFFFFFh Enable bits for the individual FROs. A '1' in bit [n] enables FRO 'n'. Default state is all '1's to enable all FROs after power-up. Note that they are not actually started up before the CTL.TRNG_EN bit is set to '1'.
Bits are automatically forced to '0' here (and cannot be written to '1') while the corresponding bit in ALARMSTOP.FRO_FLAGS has value '1'.

19.7.1.10 FRODETUNE Register (Offset = 24h) [Reset = 00000000h]

FRODETUNE is shown in #TRNG_TRNG_MAP1_TRNG_ALL_FRODETUNE_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_FRODETUNE_TABLE.

Return to the Summary Table.

FRO De-tune Bit

Figure 19-13 FRODETUNE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED FRO_MASK
R-0h R/W-0h
Table 19-16 FRODETUNE Register Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h Reserved
23-0 FRO_MASK R/W 0h De-tune bits for the individual FROs. A '1' in bit [n] lets FRO 'n' run approximately 5% faster. The value of one of these bits may only be changed while the corresponding FRO is turned off (by temporarily writing a '0' in the corresponding
bit of the FROEN.FRO_MASK register).

19.7.1.11 ALARMMASK Register (Offset = 28h) [Reset = 00000000h]

ALARMMASK is shown in #TRNG_TRNG_MAP1_TRNG_ALL_ALARMMASK_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_ALARMMASK_TABLE.

Return to the Summary Table.

Alarm Event

Figure 19-14 ALARMMASK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED FRO_MASK
R-0h R/W-0h
Table 19-17 ALARMMASK Register Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h Reserved
23-0 FRO_MASK R/W 0h Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] indicates FRO 'n' experienced an 'alarm event'.

19.7.1.12 ALARMSTOP Register (Offset = 2Ch) [Reset = 00000000h]

ALARMSTOP is shown in #TRNG_TRNG_MAP1_TRNG_ALL_ALARMSTOP_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_ALARMSTOP_TABLE.

Return to the Summary Table.

Alarm Shutdown

Figure 19-15 ALARMSTOP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED FRO_FLAGS
R-0h R/W-0h
Table 19-18 ALARMSTOP Register Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h Reserved
23-0 FRO_FLAGS R/W 0h Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] indicates FRO 'n' experienced more than one 'alarm event' in quick succession and has been turned off. A '1' in this field forces the corresponding bit in FROEN.FRO_MASK to '0'.

19.7.1.13 LFSR0 Register (Offset = 30h) [Reset = 00000000h]

LFSR0 is shown in #TRNG_TRNG_MAP1_TRNG_ALL_LFSR0_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_LFSR0_TABLE.

Return to the Summary Table.

LFSR Readout Value

Figure 19-16 LFSR0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSR_31_0
R/W-0h
Table 19-19 LFSR0 Register Field Descriptions
Bit Field Type Reset Description
31-0 LFSR_31_0 R/W 0h Bits [31:0] of the main entropy accumulation LFSR. Register can only be accessed when CTL.TEST_MODE = 1.
Register contents will be cleared to zero before access is enabled.

19.7.1.14 LFSR1 Register (Offset = 34h) [Reset = 00000000h]

LFSR1 is shown in #TRNG_TRNG_MAP1_TRNG_ALL_LFSR1_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_LFSR1_TABLE.

Return to the Summary Table.

LFSR Readout Value

Figure 19-17 LFSR1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSR_63_32
R/W-0h
Table 19-20 LFSR1 Register Field Descriptions
Bit Field Type Reset Description
31-0 LFSR_63_32 R/W 0h Bits [63:32] of the main entropy accumulation LFSR. Register can only be accessed when CTL.TEST_MODE = 1.
Register contents will be cleared to zero before access is enabled.

19.7.1.15 LFSR2 Register (Offset = 38h) [Reset = 00000000h]

LFSR2 is shown in #TRNG_TRNG_MAP1_TRNG_ALL_LFSR2_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_LFSR2_TABLE.

Return to the Summary Table.

LFSR Readout Value

Figure 19-18 LFSR2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LFSR_80_64
R-0h R/W-0h
Table 19-21 LFSR2 Register Field Descriptions
Bit Field Type Reset Description
31-17 RESERVED R 0h Reserved
16-0 LFSR_80_64 R/W 0h Bits [80:64] of the main entropy accumulation LFSR. Register can only be accessed when CTL.TEST_MODE = 1.
Register contents will be cleared to zero before access is enabled.

19.7.1.16 HWOPT Register (Offset = 78h) [Reset = 00000600h]

HWOPT is shown in #TRNG_TRNG_MAP1_TRNG_ALL_HWOPT_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_HWOPT_TABLE.

Return to the Summary Table.

TRNG Engine Options Information

Figure 19-19 HWOPT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED NR_OF_FROS RESERVED
R-0h R-18h R-0h
Table 19-22 HWOPT Register Field Descriptions
Bit Field Type Reset Description
31-12 RESERVED R 0h Reserved
11-6 NR_OF_FROS R 18h Number of FROs implemented in this TRNG, value 24 (decimal).
5-0 RESERVED R 0h Reserved

19.7.1.17 HWVER0 Register (Offset = 7Ch) [Reset = 0200B44Bh]

HWVER0 is shown in #TRNG_TRNG_MAP1_TRNG_ALL_HWVER0_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_HWVER0_TABLE.

Return to the Summary Table.

HW Version 0
EIP Number And Core Revision

Figure 19-20 HWVER0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED HW_MAJOR_VER HW_MINOR_VER HW_PATCH_LVL
R-0h R-2h R-0h R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EIP_NUM_COMPL EIP_NUM
R-B4h R-4Bh
Table 19-23 HWVER0 Register Field Descriptions
Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-24 HW_MAJOR_VER R 2h 4 bits binary encoding of the major hardware revision number.
23-20 HW_MINOR_VER R 0h 4 bits binary encoding of the minor hardware revision number.
19-16 HW_PATCH_LVL R 0h 4 bits binary encoding of the hardware patch level, initial release will carry value zero.
15-8 EIP_NUM_COMPL R B4h Bit-by-bit logic complement of bits [7:0]. This TRNG gives 0xB4.
7-0 EIP_NUM R 4Bh 8 bits binary encoding of the module number. This TRNG gives 0x4B.

19.7.1.18 IRQSTATMASK Register (Offset = 1FD8h) [Reset = 00000000h]

IRQSTATMASK is shown in #TRNG_TRNG_MAP1_TRNG_ALL_IRQSTATMASK_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_IRQSTATMASK_TABLE.

Return to the Summary Table.

Interrupt Status After Masking

Figure 19-21 IRQSTATMASK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED SHUTDOWN_OVF RDY
R-0h R-0h R-0h
Table 19-24 IRQSTATMASK Register Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R 0h Reserved
1 SHUTDOWN_OVF R 0h Shutdown Overflow (result of IRQFLAGSTAT.SHUTDOWN_OVF AND'ed with IRQFLAGMASK.SHUTDOWN_OVF)
0 RDY R 0h New random value available (result of IRQFLAGSTAT.RDY AND'ed with IRQFLAGMASK.RDY)

19.7.1.19 HWVER1 Register (Offset = 1FE0h) [Reset = 00000020h]

HWVER1 is shown in #TRNG_TRNG_MAP1_TRNG_ALL_HWVER1_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_HWVER1_TABLE.

Return to the Summary Table.

HW Version 1
TRNG Revision Number

Figure 19-22 HWVER1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED REV
R-0h R-20h
Table 19-25 HWVER1 Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h Reserved
7-0 REV R 20h The revision number of this module is Rev 2.0.

19.7.1.20 IRQSET Register (Offset = 1FECh) [Reset = 00000000h]

IRQSET is shown in #TRNG_TRNG_MAP1_TRNG_ALL_IRQSET_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_IRQSET_TABLE.

Return to the Summary Table.

Interrupt Set

Figure 19-23 IRQSET Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
R-0h
Table 19-26 IRQSET Register Field Descriptions
Bit Field Type Reset Description
31-0 RESERVED R 0h Reserved

19.7.1.21 SWRESET Register (Offset = 1FF0h) [Reset = 00000000h]

SWRESET is shown in #TRNG_TRNG_MAP1_TRNG_ALL_SWRESET_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_SWRESET_TABLE.

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SW Reset Control

Figure 19-24 SWRESET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RESET
R-0h R/W-0h
Table 19-27 SWRESET Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 RESET R/W 0h Write '1' to soft reset , reset will be low for 4-5 clock cycles. Poll to 0 for reset to be completed.

19.7.1.22 IRQSTAT Register (Offset = 1FF8h) [Reset = 00000000h]

IRQSTAT is shown in #TRNG_TRNG_MAP1_TRNG_ALL_IRQSTAT_FIGURE and described in #TRNG_TRNG_MAP1_TRNG_ALL_IRQSTAT_TABLE.

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Interrupt Status

Figure 19-25 IRQSTAT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED STAT
R-0h R-0h
Table 19-28 IRQSTAT Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 STAT R 0h TRNG Interrupt status. OR'ed version of IRQFLAGSTAT.SHUTDOWN_OVF and IRQFLAGSTAT.RDY