The Arm® Cortex®-M4F processor latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons:
- The NVIC detects that the interrupt signal is asserted and the interrupt is not active.
- The NVIC detects a rising edge on the interrupt signal.
- Software writes to the corresponding interrupt set-pending register bit, or to
the Software Trigger Interrupt Register (STIR) to make a software-generated
interrupt pending (see the NVIC_ISPR0 SETPENDn register bit or the STIR
INTID register field in Section 3.9.4).
A pending interrupt remains pending until one of the following occurs:
- The processor enters the ISR for the interrupt, changing the state of the interrupt from pending to active. Then:
- For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which can cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive.
- For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed the state of the interrupt changes to pending and active. In this case, when the processor returns from the ISR the state of the interrupt changes to pending, which can cause the processor to immediately re-enter the ISR. If the interrupt signal is not pulsed while the processor is in the ISR, when the processor returns from the ISR the state of the interrupt changes to inactive.
- Software writes to the corresponding interrupt clear-pending register bit:
- For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state of the interrupt changes to inactive.
- For a pulse interrupt, the state of the interrupt changes to inactive if the state was pending, or to active if the state was active and pending.