SWCU192 User guide | 德州仪器 TI.com.cn

SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

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        382
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                578
        
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690
1. 691
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695
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7. 713
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715
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7. 737
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761
1. 762
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    2. 780
5. 781
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800
1. 801
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3. 814
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      14. 848
    2. 849
      1. 850
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      14. 863
      15. 864
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      19. 868
      20. 869
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    1. 897
      1.        898
        
                899
        
                900
      2. 901
      3. 902
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      5. 904
    2. 905
    3. 906
    4. 907
    5. 908
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  5. 910
    1. 911
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    3. 913
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    6. 916
6. 917
  1. 918
    1. 919
      1. 920
    2. 921
    3. 922
    4. 923
  2. 924
7. 925
  1. 926
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8. 928
  1. 929
  2. 930
  3. 931
  4. 932
  5. 933
  6. 934
  7. 935
  8. 936
    1. 937
    2. 938
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  9. 941
    1. 942
    2. 943
    3. 944
  10. 945
    1. 946
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    3. 948
    4. 949
    5. 950
  11. 951
    1. 952
    2. 953
    3. 954
    4. 955
    5. 956
  12. 957
  13. 958
  14. 959
  15. 960
  16. 961
  17. 962
9. 963
  1. 964
10. 965
  1. 966
  2. 967
    1. 968
      1. 969
    2. 970
    3. 971
  3. 972
  4. 973
    1. 974
    2. 975
  5. 976
    1. 977
    2. 978
      1. 979
    3. 980
      1. 981
      2. 982
    4. 983
      1. 984
      2. 985
    5. 986
      1. 987
      2. 988
      3. 989
  6. 990
    1. 991
    2. 992
11. 993
  1. 994
  2. 995
  3. 996
997

20.8.7 AUX_TIMER2 Registers

#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_TABLE_1 lists the memory-mapped registers for the AUX_TIMER2 registers. All register offset addresses not listed in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 20-135 AUX_TIMER2 Registers

Offset	Acronym	Register Name	Section
0h	CTL	Timer Control	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CTL
4h	TARGET	Target	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_TARGET
8h	SHDWTARGET	Shadow Target	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_SHDWTARGET
Ch	CNTR	Counter	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CNTR
10h	PRECFG	Clock Prescaler Configuration	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_PRECFG
14h	EVCTL	Event Control	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_EVCTL
18h	PULSETRIG	Pulse Trigger	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_PULSETRIG
80h	CH0EVCFG	Channel 0 Event Configuration	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH0EVCFG
84h	CH0CCFG	Channel 0 Capture Configuration	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH0CCFG
88h	CH0PCC	Channel 0 Pipeline Capture Compare	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH0PCC
8Ch	CH0CC	Channel 0 Capture Compare	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH0CC
90h	CH1EVCFG	Channel 1 Event Configuration	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH1EVCFG
94h	CH1CCFG	Channel 1 Capture Configuration	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH1CCFG
98h	CH1PCC	Channel 1 Pipeline Capture Compare	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH1PCC
9Ch	CH1CC	Channel 1 Capture Compare	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH1CC
A0h	CH2EVCFG	Channel 2 Event Configuration	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH2EVCFG
A4h	CH2CCFG	Channel 2 Capture Configuration	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH2CCFG
A8h	CH2PCC	Channel 2 Pipeline Capture Compare	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH2PCC
ACh	CH2CC	Channel 2 Capture Compare	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH2CC
B0h	CH3EVCFG	Channel 3 Event Configuration	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH3EVCFG
B4h	CH3CCFG	Channel 3 Capture Configuration	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH3CCFG
B8h	CH3PCC	Channel 3 Pipeline Capture Compare	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH3PCC
BCh	CH3CC	Channel 3 Capture Compare	#AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH3CC

Complex bit access types are encoded to fit into small table cells. #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_LEGEND shows the codes that are used for access types in this section.

Table 20-136 AUX_TIMER2 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

20.8.7.1 CTL Register (Offset = 0h) [Reset = 00000000h]

CTL is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CTL_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CTL_TABLE.

Return to the Summary Table.

Timer Control

Figure 20-119 CTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED	CH3_RESET	CH2_RESET	CH1_RESET	CH0_RESET	TARGET_EN	MODE
R-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 20-137 CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6	CH3_RESET	R/W	0h	Channel 3 reset. 0: No effect. 1: Reset CH3CC, CH3PCC, CH3EVCFG, and CH3CCFG. Read returns 0.
5	CH2_RESET	R/W	0h	Channel 2 reset. 0: No effect. 1: Reset CH2CC, CH2PCC, CH2EVCFG, and CH2CCFG. Read returns 0.
4	CH1_RESET	R/W	0h	Channel 1 reset. 0: No effect. 1: Reset CH1CC, CH1PCC, CH1EVCFG, and CH1CCFG. Read returns 0.
3	CH0_RESET	R/W	0h	Channel 0 reset. 0: No effect. 1: Reset CH0CC, CH0PCC, CH0EVCFG, and CH0CCFG. Read returns 0.
2	TARGET_EN	R/W	0h	Select counter target value. You must select TARGET to use shadow target functionality. 0h = 65535 1h = TARGET.VALUE
1-0	MODE	R/W	0h	Timer mode control. The timer restarts from 0 when you set MODE to UP_ONCE, UP_PER, or UPDWN_PER. When you write MODE all internally queued updates to [CHnCC.] and TARGET clear. 0h = Disable timer. Updates to counter, channels, and events stop. 1h = Count up once. The timer increments from 0 to target value, then stops and sets MODE to DIS. 2h = Count up periodically. The timer increments from 0 to target value, repeatedly. Period = (target value + 1) timer clock period 3h = Count up and down periodically. The timer counts from 0 to target value and back to 0, repeatedly. Period = (target value * 2) * timer clock period

20.8.7.2 TARGET Register (Offset = 4h) [Reset = 00000000h]

TARGET is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_TARGET_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_TARGET_TABLE.

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Target
User defined counter target.

Figure 20-120 TARGET Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																VALUE
R-0h																R/W-0h

Table 20-138 TARGET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	VALUE	R/W	0h	16 bit user defined counter target value, which is used when selected by CTL.TARGET_EN.

20.8.7.3 SHDWTARGET Register (Offset = 8h) [Reset = 00000000h]

SHDWTARGET is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_SHDWTARGET_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_SHDWTARGET_TABLE.

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Shadow Target

Figure 20-121 SHDWTARGET Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																VALUE
R-0h																R/W-0h

Table 20-139 SHDWTARGET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	VALUE	R/W	0h	Target value for next counter period. The timer copies VALUE to TARGET.VALUE when CNTR.VALUE becomes 0. The copy does not happen when you restart the timer. This is useful to avoid period jitter in PWM applications with time-varying period, sometimes referenced as phase corrected PWM.

20.8.7.4 CNTR Register (Offset = Ch) [Reset = 00000000h]

CNTR is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CNTR_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CNTR_TABLE.

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Counter

Figure 20-122 CNTR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																VALUE
R-0h																R-0h

Table 20-140 CNTR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	VALUE	R	0h	16 bit current counter value.

20.8.7.5 PRECFG Register (Offset = 10h) [Reset = 00000000h]

PRECFG is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_PRECFG_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_PRECFG_TABLE.

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Clock Prescaler Configuration

Figure 20-123 PRECFG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								CLKDIV
R-0h																								R/W-0h

Table 20-141 PRECFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	CLKDIV	R/W	0h	Clock division. CLKDIV determines the timer clock frequency for counter, synchronization, and timer event updates. The timer clock frequency is the clock selected by AUX_SYSIF:TIMER2CLKCTL.SRC divided by (CLKDIV + 1). This inverse is the timer clock period. 0x00: Divide by 1. 0x01: Divide by 2. ... 0xFF: Divide by 256.

20.8.7.6 EVCTL Register (Offset = 14h) [Reset = 00000000h]

EVCTL is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_EVCTL_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_EVCTL_TABLE.

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Event Control
Set and clear individual events manually. Manual update of an event takes priority over automatic channel updates to the same event. You cannot set and clear an event at the same time, such requests will be neglected.
An event can be automatically cleared, set, toggled, or pulsed by each channel, listed in decreasing order of priority. The action with highest priority happens when multiple channels want to update an event at the same time.
The four events connect to the asynchronous AUX event bus:
- Event 0 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
- Event 1 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
- Event 2 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
- Event 3 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.

Figure 20-124 EVCTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
EV3_SET	EV3_CLR	EV2_SET	EV2_CLR	EV1_SET	EV1_CLR	EV0_SET	EV0_CLR
W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h

Table 20-142 EVCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	EV3_SET	W	0h	Set event 3. Write 1 to set event 3.
6	EV3_CLR	W	0h	Clear event 3. Write 1 to clear event 3.
5	EV2_SET	W	0h	Set event 2. Write 1 to set event 2.
4	EV2_CLR	W	0h	Clear event 2. Write 1 to clear event 2.
3	EV1_SET	W	0h	Set event 1. Write 1 to set event 1.
2	EV1_CLR	W	0h	Clear event 1. Write 1 to clear event 1.
1	EV0_SET	W	0h	Set event 0. Write 1 to set event 0.
0	EV0_CLR	W	0h	Clear event 0. Write 1 to clear event 0.

20.8.7.7 PULSETRIG Register (Offset = 18h) [Reset = 00000000h]

PULSETRIG is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_PULSETRIG_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_PULSETRIG_TABLE.

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Pulse Trigger

Figure 20-125 PULSETRIG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							TRIG
R-0h							W-0h

Table 20-143 PULSETRIG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	TRIG	W	0h	Pulse trigger. Write 1 to generate a pulse to AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. Pulse width equals the duty cycle of AUX_SYSIF:TIMER2CLKCTL.SRC.

20.8.7.8 CH0EVCFG Register (Offset = 80h) [Reset = 00000000h]

CH0EVCFG is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH0EVCFG_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH0EVCFG_TABLE.

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Channel 0 Event Configuration
This register configures channel function and enables event outputs.
Each channel has an edge-detection circuit with memory. The circuit is:
- enabled while CCACT selects a capture function and CTL.MODE is different from DIS.
- flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode.

The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.

Figure 20-126 CH0EVCFG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
EV3_GEN	EV2_GEN	EV1_GEN	EV0_GEN	CCACT
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 20-144 CH0EVCFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	EV3_GEN	R/W	0h	Event 3 enable. 0: Channel 0 does not control event 3. 1: Channel 0 controls event 3. When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event.
6	EV2_GEN	R/W	0h	Event 2 enable. 0: Channel 0 does not control event 2. 1: Channel 0 controls event 2. When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event.
5	EV1_GEN	R/W	0h	Event 1 enable. 0: Channel 0 does not control event 1. 1: Channel 0 controls event 1. When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event.
4	EV0_GEN	R/W	0h	Event 0 enable. 0: Channel 0 does not control event 0. 1: Channel 0 controls event 0. When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event.
3-0	CCACT	R/W	0h	Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. 0h = Disable channel. 1h = Set on capture, and then disable channel. Channel function sequence: - Set enabled events on capture event and copy CNTR.VALUE to CH0CC.VALUE. - Disable channel. Primary use scenario is to select this function before you start the timer. Follow these steps if you need to select this function while CTL.MODE is different from DIS: - Set CCACT to SET_ON_CAPT with no event enable. - Configure CH0CCFG (optional). - Wait for three timer clock periods as defined in PRECFG before you set CCACT to SET_ON_CAPT_DIS. Event enable is optional. These steps prevent capture events caused by expired signal values in edge-detection circuit. 2h = Clear on zero, toggle on compare, and then disable channel. Channel function sequence: - Clear enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH0CC.VALUE = CNTR.VALUE. - Disable channel. Enabled events are set when CH0CC.VALUE = 0 and CNTR.VALUE = 0. 3h = Set on zero, toggle on compare, and then disable channel. Channel function sequence: - Set enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH0CC.VALUE = CNTR.VALUE. - Disable channel. Enabled events are cleared when CH0CC.VALUE = 0 and CNTR.VALUE = 0. 4h = Clear on compare, and then disable channel. Channel function sequence: - Clear enabled events when CH0CC.VALUE = CNTR.VALUE. - Disable channel. 5h = Set on compare, and then disable channel. Channel function sequence: - Set enabled events when CH0CC.VALUE = CNTR.VALUE. - Disable channel. 6h = Toggle on compare, and then disable channel. Channel function sequence: - Toggle enabled events when CH0CC.VALUE = CNTR.VALUE. - Disable channel. 7h = Pulse on compare, and then disable channel. Channel function sequence: - Pulse enabled events when CH0CC.VALUE = CNTR.VALUE. - Disable channel. The event is high for two timer clock periods. 8h = Period and pulse width measurement. Continuously capture period and pulse width of the signal selected by CH0CCFG.CAPT_SRC relative to the signal edge given by CH0CCFG.EDGE. Set enabled events when CH0CC.VALUE contains signal period and CH0PCC.VALUE contains signal pulse width. Notes: - Make sure that you configure CH0CCFG.CAPT_SRC and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER. - The counter restarts in the selected timer mode when CH0CC.VALUE contains the signal period. - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target. - If you want to observe a timeout event configure another channel to SET_ON_CAPT. Signal property requirements: - Signal Period >= 2 * ( 1 + PRECFG.CLKDIV ) * timer clock period. - Signal Period <= 65535 * (1 + PRECFG.CLKDIV ) * timer clock period. - Signal low and high phase >= (1 + PRECFG.CLKDIV ) * timer clock period. 9h = Set on capture repeatedly. Channel function sequence: - Set enabled events on capture event and copy CNTR.VALUE to CH0CC.VALUE. Primary use scenario is to select this function before you start the timer. Follow these steps if you need to select this function while CTL.MODE is different from DIS: - Select this function with no event enable. - Configure CH0CCFG (optional). - Wait for three timer clock periods as defined in PRECFG before you enable events. These steps prevent capture events caused by expired signal values in edge-detection circuit. Ah = Clear on zero, toggle on compare repeatedly. Channel function sequence: - Clear enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH0CC.VALUE = CNTR.VALUE. Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by: When CH0CC.VALUE <= TARGET.VALUE: Duty cycle = 1 - ( CH0CC.VALUE / TARGET.VALUE ). When CH0CC.VALUE > TARGET.VALUE: Duty cycle = 0. Enabled events are set when CH0CC.VALUE = 0 and CNTR.VALUE = 0. Bh = Set on zero, toggle on compare repeatedly. Channel function sequence: - Set enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH0CC.VALUE = CNTR.VALUE. Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by: When CH0CC.VALUE <= TARGET.VALUE: Duty cycle = CH0CC.VALUE / ( TARGET.VALUE + 1 ). When CH0CC.VALUE > TARGET.VALUE: Duty cycle = 1. Enabled events are cleared when CH0CC.VALUE = 0 and CNTR.VALUE = 0. Ch = Clear on compare repeatedly. Channel function sequence: - Clear enabled events when CH0CC.VALUE = CNTR.VALUE. Dh = Set on compare repeatedly. Channel function sequence: - Set enabled events when CH0CC.VALUE = CNTR.VALUE. Eh = Toggle on compare repeatedly. Channel function sequence: - Toggle enabled events when CH0CC.VALUE = CNTR.VALUE. Fh = Pulse on compare repeatedly. Channel function sequence: - Pulse enabled events when CH0CC.VALUE = CNTR.VALUE. The event is high for two timer clock periods.

20.8.7.9 CH0CCFG Register (Offset = 84h) [Reset = 00000000h]

CH0CCFG is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH0CCFG_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH0CCFG_TABLE.

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Channel 0 Capture Configuration

Figure 20-127 CH0CCFG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED	CAPT_SRC						EDGE
R-0h	R/W-0h						R/W-0h

Table 20-145 CH0CCFG Register Field Descriptions

Bit

Field

Type

Reset

Description

31-7

RESERVED

Reserved

6-1

CAPT_SRC

R/W

Select capture signal source from the asynchronous AUX event bus.
The selected signal enters the edge-detection circuit. False capture events can occur when:
- the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described in CH0EVCFG
- this register is reconfigured while CTL.MODE is different from DIS.
You can avoid false capture events. When wanted channel function is:
- SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH0EVCFG.CCACT.
- SET_ON_CAPT, see description for SET_ON_CAPT in CH0EVCFG.CCACT.
- PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in CH0EVCFG.CCACT.
If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read.

0h = AUX_EVCTL:EVSTAT0.AUXIO0

1h = AUX_EVCTL:EVSTAT0.AUXIO1

2h = AUX_EVCTL:EVSTAT0.AUXIO2

3h = AUX_EVCTL:EVSTAT0.AUXIO3

4h = AUX_EVCTL:EVSTAT0.AUXIO4

5h = AUX_EVCTL:EVSTAT0.AUXIO5

6h = AUX_EVCTL:EVSTAT0.AUXIO6

7h = AUX_EVCTL:EVSTAT0.AUXIO7

8h = AUX_EVCTL:EVSTAT0.AUXIO8

9h = AUX_EVCTL:EVSTAT0.AUXIO9

Ah = AUX_EVCTL:EVSTAT0.AUXIO10

Bh = AUX_EVCTL:EVSTAT0.AUXIO11

Ch = AUX_EVCTL:EVSTAT0.AUXIO12

Dh = AUX_EVCTL:EVSTAT0.AUXIO13

Eh = AUX_EVCTL:EVSTAT0.AUXIO14

Fh = AUX_EVCTL:EVSTAT0.AUXIO15

10h = AUX_EVCTL:EVSTAT1.AUXIO16

11h = AUX_EVCTL:EVSTAT1.AUXIO17

12h = AUX_EVCTL:EVSTAT1.AUXIO18

13h = AUX_EVCTL:EVSTAT1.AUXIO19

14h = AUX_EVCTL:EVSTAT1.AUXIO20

15h = AUX_EVCTL:EVSTAT1.AUXIO21

16h = AUX_EVCTL:EVSTAT1.AUXIO22

17h = AUX_EVCTL:EVSTAT1.AUXIO23

18h = AUX_EVCTL:EVSTAT1.AUXIO24

19h = AUX_EVCTL:EVSTAT1.AUXIO25

1Ah = AUX_EVCTL:EVSTAT1.AUXIO26

1Bh = AUX_EVCTL:EVSTAT1.AUXIO27

1Ch = AUX_EVCTL:EVSTAT1.AUXIO28

1Dh = AUX_EVCTL:EVSTAT1.AUXIO29

1Eh = AUX_EVCTL:EVSTAT1.AUXIO30

1Fh = AUX_EVCTL:EVSTAT1.AUXIO31

20h = AUX_EVCTL:EVSTAT2.MANUAL_EV

21h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2

22h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY

23h = AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ

24h = AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD

25h = AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD

26h = AUX_EVCTL:EVSTAT2.SCLK_LF

27h = AUX_EVCTL:EVSTAT2.PWR_DWN

28h = AUX_EVCTL:EVSTAT2.MCU_ACTIVE

29h = AUX_EVCTL:EVSTAT2.VDDR_RECHARGE

2Ah = AUX_EVCTL:EVSTAT2.ACLK_REF

2Bh = AUX_EVCTL:EVSTAT2.MCU_EV

2Ch = AUX_EVCTL:EVSTAT2.MCU_OBSMUX0

2Dh = AUX_EVCTL:EVSTAT2.MCU_OBSMUX1

2Eh = AUX_EVCTL:EVSTAT2.AUX_COMPA

2Fh = AUX_EVCTL:EVSTAT2.AUX_COMPB

30h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0

31h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1

32h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2

33h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3

35h = AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV

36h = AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV

37h = AUX_EVCTL:EVSTAT3.AUX_TDC_DONE

38h = AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N

39h = AUX_EVCTL:EVSTAT3.AUX_ADC_DONE

3Ah = AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ

3Bh = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL

3Ch = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY

3Dh = AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE

3Fh = No event.

EDGE

R/W

Edge configuration.
Channel captures counter value at selected edge on signal source selected by CAPT_SRC. See CH0EVCFG.CCACT.

0h = Capture CNTR.VALUE at falling edge of CAPT_SRC.

1h = Capture CNTR.VALUE at rising edge of CAPT_SRC.

20.8.7.10 CH0PCC Register (Offset = 88h) [Reset = 00000000h]

CH0PCC is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH0PCC_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH0PCC_TABLE.

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Channel 0 Pipeline Capture Compare

Figure 20-128 CH0PCC Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																VALUE
R-0h																R/W-0h

Table 20-146 CH0PCC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	VALUE	R/W	0h	Pipeline Capture Compare value. 16-bit user defined pipeline compare value or channel-updated capture value. Compare mode: An update of VALUE will be transferred to CH0CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When CH0EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the width of the low or high phase of the selected signal. This is specified by CH0CCFG.EDGE and CH0CCFG.CAPT_SRC.

20.8.7.11 CH0CC Register (Offset = 8Ch) [Reset = 00000000h]

CH0CC is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH0CC_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH0CC_TABLE.

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Channel 0 Capture Compare

Figure 20-129 CH0CC Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																VALUE
R-0h																R/W-0h

Table 20-147 CH0CC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	VALUE	R/W	0h	Capture Compare value. 16-bit user defined compare value or channel-updated capture value. Compare mode: VALUE is compared against CNTR.VALUE and an event is generated as specified by CH0EVCFG.CCACT when these are equal. Capture mode: The current counter value is stored in VALUE when a capture event occurs. CH0EVCFG.CCACT determines if VALUE is a signal period or a regular capture value.

20.8.7.12 CH1EVCFG Register (Offset = 90h) [Reset = 00000000h]

CH1EVCFG is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH1EVCFG_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH1EVCFG_TABLE.

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Channel 1 Event Configuration
This register configures channel function and enables event outputs.
Each channel has an edge-detection circuit with memory. The circuit is:
- enabled while CCACT selects a capture function and CTL.MODE is different from DIS.
- flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode.

The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.

Figure 20-130 CH1EVCFG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
EV3_GEN	EV2_GEN	EV1_GEN	EV0_GEN	CCACT
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 20-148 CH1EVCFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	EV3_GEN	R/W	0h	Event 3 enable. 0: Channel 1 does not control event 3. 1: Channel 1 controls event 3. When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event.
6	EV2_GEN	R/W	0h	Event 2 enable. 0: Channel 1 does not control event 2. 1: Channel 1 controls event 2. When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event.
5	EV1_GEN	R/W	0h	Event 1 enable. 0: Channel 1 does not control event 1. 1: Channel 1 controls event 1. When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event.
4	EV0_GEN	R/W	0h	Event 0 enable. 0: Channel 1 does not control event 0. 1: Channel 1 controls event 0. When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event.
3-0	CCACT	R/W	0h	Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. 0h = Disable channel. 1h = Set on capture, and then disable channel. Channel function sequence: - Set enabled events on capture event and copy CNTR.VALUE to CH1CC.VALUE. - Disable channel. Primary use scenario is to select this function before you start the timer. Follow these steps if you need to select this function while CTL.MODE is different from DIS: - Set CCACT to SET_ON_CAPT with no event enable. - Configure CH1CCFG (optional). - Wait for three timer clock periods as defined in PRECFG before you set CCACT to SET_ON_CAPT_DIS. Event enable is optional. These steps prevent capture events caused by expired signal values in edge-detection circuit. 2h = Clear on zero, toggle on compare, and then disable channel. Channel function sequence: - Clear enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH1CC.VALUE = CNTR.VALUE. - Disable channel. Enabled events are set when CH1CC.VALUE = 0 and CNTR.VALUE = 0. 3h = Set on zero, toggle on compare, and then disable channel. Channel function sequence: - Set enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH1CC.VALUE = CNTR.VALUE. - Disable channel. Enabled events are cleared when CH1CC.VALUE = 0 and CNTR.VALUE = 0. 4h = Clear on compare, and then disable channel. Channel function sequence: - Clear enabled events when CH1CC.VALUE = CNTR.VALUE. - Disable channel. 5h = Set on compare, and then disable channel. Channel function sequence: - Set enabled events when CH1CC.VALUE = CNTR.VALUE. - Disable channel. 6h = Toggle on compare, and then disable channel. Channel function sequence: - Toggle enabled events when CH1CC.VALUE = CNTR.VALUE. - Disable channel. 7h = Pulse on compare, and then disable channel. Channel function sequence: - Pulse enabled events when CH1CC.VALUE = CNTR.VALUE. - Disable channel. The event is high for two timer clock periods. 8h = Period and pulse width measurement. Continuously capture period and pulse width of the signal selected by CH1CCFG.CAPT_SRC relative to the signal edge given by CH1CCFG.EDGE. Set enabled events when CH1CC.VALUE contains signal period and CH1PCC.VALUE contains signal pulse width. Notes: - Make sure that you configure CH1CCFG.CAPT_SRC and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER. - The counter restarts in the selected timer mode when CH1CC.VALUE contains the signal period. - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target. - If you want to observe a timeout event configure another channel to SET_ON_CAPT. Signal property requirements: - Signal Period >= 2 * ( 1 + PRECFG.CLKDIV ) * timer clock period. - Signal Period <= 65535 * (1 + PRECFG.CLKDIV ) * timer clock period. - Signal low and high phase >= (1 + PRECFG.CLKDIV ) * timer clock period. 9h = Set on capture repeatedly. Channel function sequence: - Set enabled events on capture event and copy CNTR.VALUE to CH1CC.VALUE. Primary use scenario is to select this function before you start the timer. Follow these steps if you need to select this function while CTL.MODE is different from DIS: - Select this function with no event enable. - Configure CH1CCFG (optional). - Wait for three timer clock periods as defined in PRECFG before you enable events. These steps prevent capture events caused by expired signal values in edge-detection circuit. Ah = Clear on zero, toggle on compare repeatedly. Channel function sequence: - Clear enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH1CC.VALUE = CNTR.VALUE. Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by: When CH1CC.VALUE <= TARGET.VALUE: Duty cycle = 1 - ( CH1CC.VALUE / TARGET.VALUE ). When CH1CC.VALUE > TARGET.VALUE: Duty cycle = 0. Enabled events are set when CH1CC.VALUE = 0 and CNTR.VALUE = 0. Bh = Set on zero, toggle on compare repeatedly. Channel function sequence: - Set enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH1CC.VALUE = CNTR.VALUE. Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by: When CH1CC.VALUE <= TARGET.VALUE: Duty cycle = CH1CC.VALUE / ( TARGET.VALUE + 1 ). When CH1CC.VALUE > TARGET.VALUE: Duty cycle = 1. Enabled events are cleared when CH1CC.VALUE = 0 and CNTR.VALUE = 0. Ch = Clear on compare repeatedly. Channel function sequence: - Clear enabled events when CH1CC.VALUE = CNTR.VALUE. Dh = Set on compare repeatedly. Channel function sequence: - Set enabled events when CH1CC.VALUE = CNTR.VALUE. Eh = Toggle on compare repeatedly. Channel function sequence: - Toggle enabled events when CH1CC.VALUE = CNTR.VALUE. Fh = Pulse on compare repeatedly. Channel function sequence: - Pulse enabled events when CH1CC.VALUE = CNTR.VALUE. The event is high for two timer clock periods.

20.8.7.13 CH1CCFG Register (Offset = 94h) [Reset = 00000000h]

CH1CCFG is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH1CCFG_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH1CCFG_TABLE.

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Channel 1 Capture Configuration

Figure 20-131 CH1CCFG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED	CAPT_SRC						EDGE
R-0h	R/W-0h						R/W-0h

Table 20-149 CH1CCFG Register Field Descriptions

Bit

Field

Type

Reset

Description

31-7

RESERVED

Reserved

6-1

CAPT_SRC

R/W

Select capture signal source from the asynchronous AUX event bus.
The selected signal enters the edge-detection circuit. False capture events can occur when:
- the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described in CH1EVCFG
- this register is reconfigured while CTL.MODE is different from DIS.
You can avoid false capture events. When wanted channel function is:
- SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH1EVCFG.CCACT.
- SET_ON_CAPT, see description for SET_ON_CAPT in CH1EVCFG.CCACT.
- PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in CH1EVCFG.CCACT.
If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read.

0h = AUX_EVCTL:EVSTAT0.AUXIO0

1h = AUX_EVCTL:EVSTAT0.AUXIO1

2h = AUX_EVCTL:EVSTAT0.AUXIO2

3h = AUX_EVCTL:EVSTAT0.AUXIO3

4h = AUX_EVCTL:EVSTAT0.AUXIO4

5h = AUX_EVCTL:EVSTAT0.AUXIO5

6h = AUX_EVCTL:EVSTAT0.AUXIO6

7h = AUX_EVCTL:EVSTAT0.AUXIO7

8h = AUX_EVCTL:EVSTAT0.AUXIO8

9h = AUX_EVCTL:EVSTAT0.AUXIO9

Ah = AUX_EVCTL:EVSTAT0.AUXIO10

Bh = AUX_EVCTL:EVSTAT0.AUXIO11

Ch = AUX_EVCTL:EVSTAT0.AUXIO12

Dh = AUX_EVCTL:EVSTAT0.AUXIO13

Eh = AUX_EVCTL:EVSTAT0.AUXIO14

Fh = AUX_EVCTL:EVSTAT0.AUXIO15

10h = AUX_EVCTL:EVSTAT1.AUXIO16

11h = AUX_EVCTL:EVSTAT1.AUXIO17

12h = AUX_EVCTL:EVSTAT1.AUXIO18

13h = AUX_EVCTL:EVSTAT1.AUXIO19

14h = AUX_EVCTL:EVSTAT1.AUXIO20

15h = AUX_EVCTL:EVSTAT1.AUXIO21

16h = AUX_EVCTL:EVSTAT1.AUXIO22

17h = AUX_EVCTL:EVSTAT1.AUXIO23

18h = AUX_EVCTL:EVSTAT1.AUXIO24

19h = AUX_EVCTL:EVSTAT1.AUXIO25

1Ah = AUX_EVCTL:EVSTAT1.AUXIO26

1Bh = AUX_EVCTL:EVSTAT1.AUXIO27

1Ch = AUX_EVCTL:EVSTAT1.AUXIO28

1Dh = AUX_EVCTL:EVSTAT1.AUXIO29

1Eh = AUX_EVCTL:EVSTAT1.AUXIO30

1Fh = AUX_EVCTL:EVSTAT1.AUXIO31

20h = AUX_EVCTL:EVSTAT2.MANUAL_EV

21h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2

22h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY

23h = AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ

24h = AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD

25h = AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD

26h = AUX_EVCTL:EVSTAT2.SCLK_LF

27h = AUX_EVCTL:EVSTAT2.PWR_DWN

28h = AUX_EVCTL:EVSTAT2.MCU_ACTIVE

29h = AUX_EVCTL:EVSTAT2.VDDR_RECHARGE

2Ah = AUX_EVCTL:EVSTAT2.ACLK_REF

2Bh = AUX_EVCTL:EVSTAT2.MCU_EV

2Ch = AUX_EVCTL:EVSTAT2.MCU_OBSMUX0

2Dh = AUX_EVCTL:EVSTAT2.MCU_OBSMUX1

2Eh = AUX_EVCTL:EVSTAT2.AUX_COMPA

2Fh = AUX_EVCTL:EVSTAT2.AUX_COMPB

30h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0

31h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1

32h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2

33h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3

35h = AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV

36h = AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV

37h = AUX_EVCTL:EVSTAT3.AUX_TDC_DONE

38h = AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N

39h = AUX_EVCTL:EVSTAT3.AUX_ADC_DONE

3Ah = AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ

3Bh = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL

3Ch = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY

3Dh = AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE

3Fh = No event.

EDGE

R/W

Edge configuration.
Channel captures counter value at selected edge on signal source selected by CAPT_SRC. See CH1EVCFG.CCACT.

0h = Capture CNTR.VALUE at falling edge of CAPT_SRC.

1h = Capture CNTR.VALUE at rising edge of CAPT_SRC.

20.8.7.14 CH1PCC Register (Offset = 98h) [Reset = 00000000h]

CH1PCC is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH1PCC_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH1PCC_TABLE.

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Channel 1 Pipeline Capture Compare

Figure 20-132 CH1PCC Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																VALUE
R-0h																R/W-0h

Table 20-150 CH1PCC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	VALUE	R/W	0h	Pipeline Capture Compare value. 16-bit user defined pipeline compare value or channel-updated capture value. Compare mode: An update of VALUE will be transferred to CH1CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When CH1EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the width of the low or high phase of the selected signal. This is specified by CH1CCFG.EDGE and CH1CCFG.CAPT_SRC.

20.8.7.15 CH1CC Register (Offset = 9Ch) [Reset = 00000000h]

CH1CC is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH1CC_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH1CC_TABLE.

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Channel 1 Capture Compare

Figure 20-133 CH1CC Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																VALUE
R-0h																R/W-0h

Table 20-151 CH1CC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	VALUE	R/W	0h	Capture Compare value. 16-bit user defined compare value or channel-updated capture value. Compare mode: VALUE is compared against CNTR.VALUE and an event is generated as specified by CH1EVCFG.CCACT when these are equal. Capture mode: The current counter value is stored in VALUE when a capture event occurs. CH1EVCFG.CCACT determines if VALUE is a signal period or a regular capture value.

20.8.7.16 CH2EVCFG Register (Offset = A0h) [Reset = 00000000h]

CH2EVCFG is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH2EVCFG_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH2EVCFG_TABLE.

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Channel 2 Event Configuration
This register configures channel function and enables event outputs.
Each channel has an edge-detection circuit with memory. The circuit is:
- enabled while CCACT selects a capture function and CTL.MODE is different from DIS.
- flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode.

The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.

Figure 20-134 CH2EVCFG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
EV3_GEN	EV2_GEN	EV1_GEN	EV0_GEN	CCACT
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 20-152 CH2EVCFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	EV3_GEN	R/W	0h	Event 3 enable. 0: Channel 2 does not control event 3. 1: Channel 2 controls event 3. When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event.
6	EV2_GEN	R/W	0h	Event 2 enable. 0: Channel 2 does not control event 2. 1: Channel 2 controls event 2. When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event.
5	EV1_GEN	R/W	0h	Event 1 enable. 0: Channel 2 does not control event 1. 1: Channel 2 controls event 1. When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event.
4	EV0_GEN	R/W	0h	Event 0 enable. 0: Channel 2 does not control event 0. 1: Channel 2 controls event 0. When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event.
3-0	CCACT	R/W	0h	Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. 0h = Disable channel. 1h = Set on capture, and then disable channel. Channel function sequence: - Set enabled events on capture event and copy CNTR.VALUE to CH2CC.VALUE. - Disable channel. Primary use scenario is to select this function before you start the timer. Follow these steps if you need to select this function while CTL.MODE is different from DIS: - Set to SET_ON_CAPT with no event enable. - Configure CH2CCFG (optional). - Wait for three timer clock periods as defined in PRECFG before you set to SET_ON_CAPT_DIS. Event enable is optional. These steps prevent capture events caused by expired signal values in edge-detection circuit. 2h = Clear on zero, toggle on compare, and then disable channel. Channel function sequence: - Clear enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH2CC.VALUE = CNTR.VALUE. - Disable channel. Enabled events are set when CH2CC.VALUE = 0 and CNTR.VALUE = 0. 3h = Set on zero, toggle on compare, and then disable channel. Channel function sequence: - Set enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH2CC.VALUE = CNTR.VALUE. - Disable channel. Enabled events are cleared when CH2CC.VALUE = 0 and CNTR.VALUE = 0. 4h = Clear on compare, and then disable channel. Channel function sequence: - Clear enabled events when CH2CC.VALUE = CNTR.VALUE. - Disable channel. 5h = Set on compare, and then disable channel. Channel function sequence: - Set enabled events when CH2CC.VALUE = CNTR.VALUE. - Disable channel. 6h = Toggle on compare, and then disable channel. Channel function sequence: - Toggle enabled events when CH2CC.VALUE = CNTR.VALUE. - Disable channel. 7h = Pulse on compare, and then disable channel. Channel function sequence: - Pulse enabled events when CH2CC.VALUE = CNTR.VALUE. - Disable channel. The event is high for two timer clock periods. 8h = Period and pulse width measurement. Continuously capture period and pulse width of the signal selected by CH2CCFG.CAPT_SRC relative to the signal edge given by CH2CCFG.EDGE. Set enabled events when CH2CC.VALUE contains signal period and CH2PCC.VALUE contains signal pulse width. Notes: - Make sure that you configure CH2CCFG.CAPT_SRC and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER. - The counter restarts in the selected timer mode when CH2CC.VALUE contains the signal period. - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target. - If you want to observe a timeout event configure another channel to SET_ON_CAPT. Signal property requirements: - Signal Period >= 2 * ( 1 + PRECFG.CLKDIV ) * timer clock period. - Signal Period <= 65535 * (1 + PRECFG.CLKDIV ) * timer clock period. - Signal low and high phase >= (1 + PRECFG.CLKDIV ) * timer clock period. 9h = Set on capture repeatedly. Channel function sequence: - Set enabled events on capture event and copy CNTR.VALUE to CH2CC.VALUE. Primary use scenario is to select this function before you start the timer. Follow these steps if you need to select this function while CTL.MODE is different from DIS: - Select this function with no event enable. - Configure CH2CCFG (optional). - Wait for three timer clock periods as defined in PRECFG before you enable events. These steps prevent capture events caused by expired signal values in edge-detection circuit. Ah = Clear on zero, toggle on compare repeatedly. Channel function sequence: - Clear enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH2CC.VALUE = CNTR.VALUE. Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by: When CH2CC.VALUE <= TARGET.VALUE: Duty cycle = 1 - ( CH2CC.VALUE / TARGET.VALUE ). When CH2CC.VALUE > TARGET.VALUE: Duty cycle = 0. Enabled events are set when CH2CC.VALUE = 0 and CNTR.VALUE = 0. Bh = Set on zero, toggle on compare repeatedly. Channel function sequence: - Set enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH2CC.VALUE = CNTR.VALUE. Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by: When CH2CC.VALUE <= TARGET.VALUE: Duty cycle = CH2CC.VALUE / ( TARGET.VALUE + 1 ). When CH2CC.VALUE > TARGET.VALUE: Duty cycle = 1. Enabled events are cleared when CH2CC.VALUE = 0 and CNTR.VALUE = 0. Ch = Clear on compare repeatedly. Channel function sequence: - Clear enabled events when CH2CC.VALUE = CNTR.VALUE. Dh = Set on compare repeatedly. Channel function sequence: - Set enabled events when CH2CC.VALUE = CNTR.VALUE. Eh = Toggle on compare repeatedly. Channel function sequence: - Toggle enabled events when CH2CC.VALUE = CNTR.VALUE. Fh = Pulse on compare repeatedly. Channel function sequence: - Pulse enabled events when CH2CC.VALUE = CNTR.VALUE. The event is high for two timer clock periods.

20.8.7.17 CH2CCFG Register (Offset = A4h) [Reset = 00000000h]

CH2CCFG is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH2CCFG_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH2CCFG_TABLE.

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Channel 2 Capture Configuration

Figure 20-135 CH2CCFG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED	CAPT_SRC						EDGE
R-0h	R/W-0h						R/W-0h

Table 20-153 CH2CCFG Register Field Descriptions

Bit

Field

Type

Reset

Description

31-7

RESERVED

Reserved

6-1

CAPT_SRC

R/W

Select capture signal source from the asynchronous AUX event bus.
The selected signal enters the edge-detection circuit. False capture events can occur when:
- the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described in CH2EVCFG
- this register is reconfigured while CTL.MODE is different from DIS.
You can avoid false capture events. When wanted channel function is:
- SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH2EVCFG.CCACT.
- SET_ON_CAPT, see description for SET_ON_CAPT in CH2EVCFG.CCACT.
- PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in CH2EVCFG.CCACT.
If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read.

0h = AUX_EVCTL:EVSTAT0.AUXIO0

1h = AUX_EVCTL:EVSTAT0.AUXIO1

2h = AUX_EVCTL:EVSTAT0.AUXIO2

3h = AUX_EVCTL:EVSTAT0.AUXIO3

4h = AUX_EVCTL:EVSTAT0.AUXIO4

5h = AUX_EVCTL:EVSTAT0.AUXIO5

6h = AUX_EVCTL:EVSTAT0.AUXIO6

7h = AUX_EVCTL:EVSTAT0.AUXIO7

8h = AUX_EVCTL:EVSTAT0.AUXIO8

9h = AUX_EVCTL:EVSTAT0.AUXIO9

Ah = AUX_EVCTL:EVSTAT0.AUXIO10

Bh = AUX_EVCTL:EVSTAT0.AUXIO11

Ch = AUX_EVCTL:EVSTAT0.AUXIO12

Dh = AUX_EVCTL:EVSTAT0.AUXIO13

Eh = AUX_EVCTL:EVSTAT0.AUXIO14

Fh = AUX_EVCTL:EVSTAT0.AUXIO15

10h = AUX_EVCTL:EVSTAT1.AUXIO16

11h = AUX_EVCTL:EVSTAT1.AUXIO17

12h = AUX_EVCTL:EVSTAT1.AUXIO18

13h = AUX_EVCTL:EVSTAT1.AUXIO19

14h = AUX_EVCTL:EVSTAT1.AUXIO20

15h = AUX_EVCTL:EVSTAT1.AUXIO21

16h = AUX_EVCTL:EVSTAT1.AUXIO22

17h = AUX_EVCTL:EVSTAT1.AUXIO23

18h = AUX_EVCTL:EVSTAT1.AUXIO24

19h = AUX_EVCTL:EVSTAT1.AUXIO25

1Ah = AUX_EVCTL:EVSTAT1.AUXIO26

1Bh = AUX_EVCTL:EVSTAT1.AUXIO27

1Ch = AUX_EVCTL:EVSTAT1.AUXIO28

1Dh = AUX_EVCTL:EVSTAT1.AUXIO29

1Eh = AUX_EVCTL:EVSTAT1.AUXIO30

1Fh = AUX_EVCTL:EVSTAT1.AUXIO31

20h = AUX_EVCTL:EVSTAT2.MANUAL_EV

21h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2

22h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY

23h = AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ

24h = AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD

25h = AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD

26h = AUX_EVCTL:EVSTAT2.SCLK_LF

27h = AUX_EVCTL:EVSTAT2.PWR_DWN

28h = AUX_EVCTL:EVSTAT2.MCU_ACTIVE

29h = AUX_EVCTL:EVSTAT2.VDDR_RECHARGE

2Ah = AUX_EVCTL:EVSTAT2.ACLK_REF

2Bh = AUX_EVCTL:EVSTAT2.MCU_EV

2Ch = AUX_EVCTL:EVSTAT2.MCU_OBSMUX0

2Dh = AUX_EVCTL:EVSTAT2.MCU_OBSMUX1

2Eh = AUX_EVCTL:EVSTAT2.AUX_COMPA

2Fh = AUX_EVCTL:EVSTAT2.AUX_COMPB

30h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0

31h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1

32h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2

33h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3

35h = AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV

36h = AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV

37h = AUX_EVCTL:EVSTAT3.AUX_TDC_DONE

38h = AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N

39h = AUX_EVCTL:EVSTAT3.AUX_ADC_DONE

3Ah = AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ

3Bh = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL

3Ch = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY

3Dh = AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE

3Fh = No event.

EDGE

R/W

Edge configuration.
Channel captures counter value at selected edge on signal source selected by CAPT_SRC. See CH2EVCFG.CCACT.

0h = Capture CNTR.VALUE at falling edge of CAPT_SRC.

1h = Capture CNTR.VALUE at rising edge of CAPT_SRC.

20.8.7.18 CH2PCC Register (Offset = A8h) [Reset = 00000000h]

CH2PCC is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH2PCC_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH2PCC_TABLE.

Return to the Summary Table.

Channel 2 Pipeline Capture Compare

Figure 20-136 CH2PCC Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																VALUE
R-0h																R/W-0h

Table 20-154 CH2PCC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	VALUE	R/W	0h	Pipeline Capture Compare value. 16-bit user defined pipeline compare value or channel-updated capture value. Compare mode: An update of VALUE will be transferred to CH2CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When CH2EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the width of the low or high phase of the selected signal. This is specified by CH2CCFG.EDGE and CH2CCFG.CAPT_SRC.

20.8.7.19 CH2CC Register (Offset = ACh) [Reset = 00000000h]

CH2CC is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH2CC_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH2CC_TABLE.

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Channel 2 Capture Compare

Figure 20-137 CH2CC Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																VALUE
R-0h																R/W-0h

Table 20-155 CH2CC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	VALUE	R/W	0h	Capture Compare value. 16-bit user defined compare value or channel-updated capture value. Compare mode: VALUE is compared against CNTR.VALUE and an event is generated as specified by CH2EVCFG.CCACT when these are equal. Capture mode: The current counter value is stored in VALUE when a capture event occurs. CH2EVCFG.CCACT determines if VALUE is a signal period or a regular capture value.

20.8.7.20 CH3EVCFG Register (Offset = B0h) [Reset = 00000000h]

CH3EVCFG is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH3EVCFG_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH3EVCFG_TABLE.

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Channel 3 Event Configuration
This register configures channel function and enables event outputs.
Each channel has an edge-detection circuit with memory. The circuit is:
- enabled while CCACT selects a capture function and CTL.MODE is different from DIS.
- flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode.

The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.

Figure 20-138 CH3EVCFG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
EV3_GEN	EV2_GEN	EV1_GEN	EV0_GEN	CCACT
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 20-156 CH3EVCFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	EV3_GEN	R/W	0h	Event 3 enable. 0: Channel 3 does not control event 3. 1: Channel 3 controls event 3. When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event.
6	EV2_GEN	R/W	0h	Event 2 enable. 0: Channel 3 does not control event 2. 1: Channel 3 controls event 2. When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event.
5	EV1_GEN	R/W	0h	Event 1 enable. 0: Channel 3 does not control event 1. 1: Channel 3 controls event 1. When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event.
4	EV0_GEN	R/W	0h	Event 0 enable. 0: Channel 3 does not control event 0. 1: Channel 3 controls event 0. When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event.
3-0	CCACT	R/W	0h	Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. 0h = Disable channel. 1h = Set on capture, and then disable channel. Channel function sequence: - Set enabled events on capture event and copy CNTR.VALUE to CH3CC.VALUE. - Disable channel. Primary use scenario is to select this function before you start the timer. Follow these steps if you need to select this function while CTL.MODE is different from DIS: - Set CCACT to SET_ON_CAPT with no event enable. - Configure CH3CCFG (optional). - Wait for three timer clock periods as defined in PRECFG before you set CCACT to SET_ON_CAPT_DIS. Event enable is optional. These steps prevent capture events caused by expired signal values in edge-detection circuit. 2h = Clear on zero, toggle on compare, and then disable channel. Channel function sequence: - Clear enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH3CC.VALUE = CNTR.VALUE. - Disable channel. Enabled events are set when CH3CC.VALUE = 0 and CNTR.VALUE = 0. 3h = Set on zero, toggle on compare, and then disable channel. Channel function sequence: - Set enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH3CC.VALUE = CNTR.VALUE. - Disable channel. Enabled events are cleared when CH3CC.VALUE = 0 and CNTR.VALUE = 0. 4h = Clear on compare, and then disable channel. Channel function sequence: - Clear enabled events when CH3CC.VALUE = CNTR.VALUE. - Disable channel. 5h = Set on compare, and then disable channel. Channel function sequence: - Set enabled events when CH3CC.VALUE = CNTR.VALUE. - Disable channel. 6h = Toggle on compare, and then disable channel. Channel function sequence: - Toggle enabled events when CH3CC.VALUE = CNTR.VALUE. - Disable channel. 7h = Pulse on compare, and then disable channel. Channel function sequence: - Pulse enabled events when CH3CC.VALUE = CNTR.VALUE. - Disable channel. The event is high for two timer clock periods. 8h = Period and pulse width measurement. Continuously capture period and pulse width of the signal selected by CH3CCFG.CAPT_SRC relative to the signal edge given by CH3CCFG.EDGE. Set enabled events when CH3CC.VALUE contains signal period and CH3PCC.VALUE contains signal pulse width. Notes: - Make sure that you configure CH3CCFG.CAPT_SRC and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER. - The counter restarts in the selected timer mode when CH3CC.VALUE contains the signal period. - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target. - If you want to observe a timeout event configure another channel to SET_ON_CAPT. Signal property requirements: - Signal Period >= 2 * ( 1 + PRECFG.CLKDIV ) * timer clock period. - Signal Period <= 65535 * (1 + PRECFG.CLKDIV ) * timer clock period. - Signal low and high phase >= (1 + PRECFG.CLKDIV ) * timer clock period. 9h = Set on capture repeatedly. Channel function sequence: - Set enabled events on capture event and copy CNTR.VALUE to CH3CC.VALUE. Primary use scenario is to select this function before you start the timer. Follow these steps if you need to select this function while CTL.MODE is different from DIS: - Select this function with no event enable. - Configure CH3CCFG (optional). - Wait for three timer clock periods as defined in PRECFG before you enable events. These steps prevent capture events caused by expired signal values in edge-detection circuit. Ah = Clear on zero, toggle on compare repeatedly. Channel function sequence: - Clear enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH3CC.VALUE = CNTR.VALUE. Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by: When CH3CC.VALUE <= TARGET.VALUE: Duty cycle = 1 - ( CH3CC.VALUE / TARGET.VALUE ). When CH3CC.VALUE > TARGET.VALUE: Duty cycle = 0. Enabled events are set when CH3CC.VALUE = 0 and CNTR.VALUE = 0. Bh = Set on zero, toggle on compare repeatedly. Channel function sequence: - Set enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH3CC.VALUE = CNTR.VALUE. Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by: When CH3CC.VALUE <= TARGET.VALUE: Duty cycle = CH3CC.VALUE / ( TARGET.VALUE + 1 ). When CH3CC.VALUE > TARGET.VALUE: Duty cycle = 1. Enabled events are cleared when CH3CC.VALUE = 0 and CNTR.VALUE = 0. Ch = Clear on compare repeatedly. Channel function sequence: - Clear enabled events when CH3CC.VALUE = CNTR.VALUE. Dh = Set on compare repeatedly. Channel function sequence: - Set enabled events when CH3CC.VALUE = CNTR.VALUE. Eh = Toggle on compare repeatedly. Channel function sequence: - Toggle enabled events when CH3CC.VALUE = CNTR.VALUE. Fh = Pulse on compare repeatedly. Channel function sequence: - Pulse enabled events when CH3CC.VALUE = CNTR.VALUE. The event is high for two timer clock periods.

20.8.7.21 CH3CCFG Register (Offset = B4h) [Reset = 00000000h]

CH3CCFG is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH3CCFG_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH3CCFG_TABLE.

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Channel 3 Capture Configuration

Figure 20-139 CH3CCFG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED	CAPT_SRC						EDGE
R-0h	R/W-0h						R/W-0h

Table 20-157 CH3CCFG Register Field Descriptions

Bit

Field

Type

Reset

Description

31-7

RESERVED

Reserved

6-1

CAPT_SRC

R/W

Select capture signal source from the asynchronous AUX event bus.
The selected signal enters the edge-detection circuit. False capture events can occur when:
- the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described in CH3EVCFG
- this register is reconfigured while CTL.MODE is different from DIS.
You can avoid false capture events. When wanted channel function:
- SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH3EVCFG.CCACT.
- SET_ON_CAPT, see description for SET_ON_CAPT in CH3EVCFG.CCACT.
- PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in CH3EVCFG.CCACT.
If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read.

0h = AUX_EVCTL:EVSTAT0.AUXIO0

1h = AUX_EVCTL:EVSTAT0.AUXIO1

2h = AUX_EVCTL:EVSTAT0.AUXIO2

3h = AUX_EVCTL:EVSTAT0.AUXIO3

4h = AUX_EVCTL:EVSTAT0.AUXIO4

5h = AUX_EVCTL:EVSTAT0.AUXIO5

6h = AUX_EVCTL:EVSTAT0.AUXIO6

7h = AUX_EVCTL:EVSTAT0.AUXIO7

8h = AUX_EVCTL:EVSTAT0.AUXIO8

9h = AUX_EVCTL:EVSTAT0.AUXIO9

Ah = AUX_EVCTL:EVSTAT0.AUXIO10

Bh = AUX_EVCTL:EVSTAT0.AUXIO11

Ch = AUX_EVCTL:EVSTAT0.AUXIO12

Dh = AUX_EVCTL:EVSTAT0.AUXIO13

Eh = AUX_EVCTL:EVSTAT0.AUXIO14

Fh = AUX_EVCTL:EVSTAT0.AUXIO15

10h = AUX_EVCTL:EVSTAT1.AUXIO16

11h = AUX_EVCTL:EVSTAT1.AUXIO17

12h = AUX_EVCTL:EVSTAT1.AUXIO18

13h = AUX_EVCTL:EVSTAT1.AUXIO19

14h = AUX_EVCTL:EVSTAT1.AUXIO20

15h = AUX_EVCTL:EVSTAT1.AUXIO21

16h = AUX_EVCTL:EVSTAT1.AUXIO22

17h = AUX_EVCTL:EVSTAT1.AUXIO23

18h = AUX_EVCTL:EVSTAT1.AUXIO24

19h = AUX_EVCTL:EVSTAT1.AUXIO25

1Ah = AUX_EVCTL:EVSTAT1.AUXIO26

1Bh = AUX_EVCTL:EVSTAT1.AUXIO27

1Ch = AUX_EVCTL:EVSTAT1.AUXIO28

1Dh = AUX_EVCTL:EVSTAT1.AUXIO29

1Eh = AUX_EVCTL:EVSTAT1.AUXIO30

1Fh = AUX_EVCTL:EVSTAT1.AUXIO31

20h = AUX_EVCTL:EVSTAT2.MANUAL_EV

21h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2

22h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY

23h = AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ

24h = AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD

25h = AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD

26h = AUX_EVCTL:EVSTAT2.SCLK_LF

27h = AUX_EVCTL:EVSTAT2.PWR_DWN

28h = AUX_EVCTL:EVSTAT2.MCU_ACTIVE

29h = AUX_EVCTL:EVSTAT2.VDDR_RECHARGE

2Ah = AUX_EVCTL:EVSTAT2.ACLK_REF

2Bh = AUX_EVCTL:EVSTAT2.MCU_EV

2Ch = AUX_EVCTL:EVSTAT2.MCU_OBSMUX0

2Dh = AUX_EVCTL:EVSTAT2.MCU_OBSMUX1

2Eh = AUX_EVCTL:EVSTAT2.AUX_COMPA

2Fh = AUX_EVCTL:EVSTAT2.AUX_COMPB

30h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0

31h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1

32h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2

33h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3

35h = AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV

36h = AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV

37h = AUX_EVCTL:EVSTAT3.AUX_TDC_DONE

38h = AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N

39h = AUX_EVCTL:EVSTAT3.AUX_ADC_DONE

3Ah = AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ

3Bh = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL

3Ch = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY

3Dh = AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE

3Fh = No event.

EDGE

R/W

Edge configuration.
Channel captures counter value at selected edge on signal source selected by CAPT_SRC. See CH3EVCFG.CCACT.

0h = Capture CNTR.VALUE at falling edge of CAPT_SRC.

1h = Capture CNTR.VALUE at rising edge of CAPT_SRC.

20.8.7.22 CH3PCC Register (Offset = B8h) [Reset = 00000000h]

CH3PCC is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH3PCC_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH3PCC_TABLE.

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Channel 3 Pipeline Capture Compare

Figure 20-140 CH3PCC Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																VALUE
R-0h																R/W-0h

Table 20-158 CH3PCC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	VALUE	R/W	0h	Pipeline Capture Compare value. 16-bit user defined pipeline compare value or channel-updated capture value. Compare mode: An update of VALUE will be transferred to CH3CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When CH3EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the width of the low or high phase of the selected signal. This is specified by CH3CCFG.EDGE and CH3CCFG.CAPT_SRC.

20.8.7.23 CH3CC Register (Offset = BCh) [Reset = 00000000h]

CH3CC is shown in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH3CC_FIGURE and described in #AUX_TIMER2_AUX_TIMER2_MMAP_AUX_TIMER2_AUX_TIMER2_ALL_CH3CC_TABLE.

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Channel 3 Capture Compare

Figure 20-141 CH3CC Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																VALUE
R-0h																R/W-0h

Table 20-159 CH3CC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	VALUE	R/W	0h	Capture Compare value. 16-bit user defined compare value or channel-updated capture value. Compare mode: VALUE is compared against CNTR.VALUE and an event is generated as specified by CH3EVCFG.CCACT when these are equal. Capture mode: The current counter value is stored in VALUE when a capture event occurs. CH3EVCFG.CCACT determines if VALUE is a signal period or a regular capture value.