SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The μDMA controller generates a completion interrupt on the interrupt vector of the peripheral when a μDMA transfer completes. Therefore, if μDMA is used to transfer data for a peripheral and interrupts are used, then the interrupt handler for that peripheral must be designed to handle the μDMA transfer completion interrupt. If the transfer uses the software μDMA channel, then the completion interrupt occurs on the dedicated software μDMA interrupt vector (see Table 15-6).
When μDMA is enabled for a peripheral, the μDMA controller stops the normal transfer interrupts for a peripheral from reaching the interrupt controller (INTC). The interrupts are still reported in the interrupt registers of the peripheral. Thus, when a large amount of data is transferred using μDMA, instead of receiving multiple interrupts from the peripheral as data flows, the INTC receives only one interrupt when the transfer completes. Unmasked peripheral error interrupts continue to be sent to the INTC.
When a μDMA channel generates a completion interrupt, the CHNLS bit corresponding to the peripheral channel is set in the DMA Channel Request Done register, UDMA:REQDONE. This register can be used by the interrupt handler code of the peripheral to determine if the interrupt was caused by the μDMA channel or an error event reported by the interrupt registers of the peripheral. The completion interrupt request from the μDMA controller is automatically cleared when the interrupt handler is activated.
If the μDMA controller encounters a bus or memory protection error as it tries to perform a data transfer, the controller disables the μDMA channel that caused the error and generates an interrupt on the μDMA error interrupt vector. The processor can read the DMA Clear Bus Error register, UDMA:ERROR, to determine if an error is pending. The STATUS bit is set if an error occurred. The error can be cleared by setting the STATUS bit to 1.
The error interrupt or event goes to the event fabric as DMA_ERR, and is connected as an interrupt to the Arm® Cortex®-M4F processor through the EVENT:CPUIRQSEL25 register.
Table 15-6 lists the dedicated interrupt assignments for the μDMA controller.
| Interrupt | Assignment |
|---|---|
| 40 | μDMA software channel transfer |
| 41 | μDMA error |