SWCU192 User guide | 德州仪器 TI.com.cn

SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

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        382
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                578
        
                579
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                602
        
                 603
        
                604
        
                 605
        
                606
        
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                637
        
                638
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                645
        
                646
        
                647
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                649
        
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                652
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                668
        
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7. 676
8. 677
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690
1. 691
2. 692
3. 693
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695
1. 696
2. 697
3. 698
4. 699
  1. 700
  2. 701
  3. 702
  4. 703
    1. 704
    2. 705
      1. 706
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  7. 710
5. 711
6. 712
7. 713
  1. 714
715
1. 716
2. 717
3. 718
4. 719
  1. 720
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    1. 726
    2. 727
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6. 736
7. 737
  1. 738
739
1. 740
2. 741
3. 742
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    1. 750
  3. 751
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  5. 755
    1. 756
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4. 758
5. 759
  1. 760
761
1. 762
2. 763
3. 764
4. 765
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    1. 767
  2. 768
  3. 769
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    1. 771
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    1. 773
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    1. 775
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    1. 777
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    1. 779
    2. 780
5. 781
  1. 782
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    1. 786
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    3. 788
6. 789
  1. 790
  2. 791
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7. 794
8. 795
  1. 796
  2. 797
9. 798
  1. 799
800
1. 801
  1. 802
2. 803
  1. 804
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  3. 806
    1. 807
    2. 808
    3. 809
  4. 810
    1. 811
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    3. 813
3. 814
  1. 815
  2. 816
    1. 817
    2. 818
    3. 819
    4. 820
    5. 821
      1. 822
      2. 823
      3. 824
    6. 825
      1. 826
    7. 827
      1. 828
      2. 829
      3. 830
      4. 831
    8. 832
  3. 833
    1. 834
      1. 835
      2. 836
      3. 837
      4. 838
      5. 839
      6. 840
      7. 841
      8. 842
      9. 843
      10. 844
      11. 845
      12. 846
      13. 847
      14. 848
    2. 849
      1. 850
      2. 851
      3. 852
      4. 853
      5. 854
      6. 855
      7. 856
      8. 857
      9. 858
      10. 859
      11. 860
      12. 861
      13. 862
      14. 863
      15. 864
      16. 865
      17. 866
      18. 867
      19. 868
      20. 869
  4. 870
    1. 871
    2. 872
    3. 873
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    5. 875
4. 876
  1. 877
    1. 878
    2. 879
    3. 880
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    5. 882
  2. 883
    1. 884
    2. 885
5. 886
  1. 887
    1. 888
    2. 889
    3. 890
    4. 891
  2. 892
  3. 893
    1. 894
    2. 895
  4. 896
    1. 897
      1.        898
        
                899
        
                900
      2. 901
      3. 902
      4. 903
      5. 904
    2. 905
    3. 906
    4. 907
    5. 908
    6. 909
  5. 910
    1. 911
    2. 912
    3. 913
    4. 914
    5. 915
    6. 916
6. 917
  1. 918
    1. 919
      1. 920
    2. 921
    3. 922
    4. 923
  2. 924
7. 925
  1. 926
  2. 927
8. 928
  1. 929
  2. 930
  3. 931
  4. 932
  5. 933
  6. 934
  7. 935
  8. 936
    1. 937
    2. 938
    3. 939
    4. 940
  9. 941
    1. 942
    2. 943
    3. 944
  10. 945
    1. 946
    2. 947
    3. 948
    4. 949
    5. 950
  11. 951
    1. 952
    2. 953
    3. 954
    4. 955
    5. 956
  12. 957
  13. 958
  14. 959
  15. 960
  16. 961
  17. 962
9. 963
  1. 964
10. 965
  1. 966
  2. 967
    1. 968
      1. 969
    2. 970
    3. 971
  3. 972
  4. 973
    1. 974
    2. 975
  5. 976
    1. 977
    2. 978
      1. 979
    3. 980
      1. 981
      2. 982
    4. 983
      1. 984
      2. 985
    5. 986
      1. 987
      2. 988
      3. 989
  6. 990
    1. 991
    2. 992
11. 993
  1. 994
  2. 995
  3. 996
997

8.8.2 PRCM Registers

#PRCM_PRCM_REGISTERS_TABLE_1 lists the memory-mapped registers for the PRCM registers. All register offset addresses not listed in #PRCM_PRCM_REGISTERS_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 8-27 PRCM Registers

Offset	Acronym	Register Name	Section
0h	INFRCLKDIVR	Infrastructure Clock Division Factor For Run Mode	#PRCM_PRCM_REGISTERS_PRCM_ALL_INFRCLKDIVR
4h	INFRCLKDIVS	Infrastructure Clock Division Factor For Sleep Mode	#PRCM_PRCM_REGISTERS_PRCM_ALL_INFRCLKDIVS
8h	INFRCLKDIVDS	Infrastructure Clock Division Factor For DeepSleep Mode	#PRCM_PRCM_REGISTERS_PRCM_ALL_INFRCLKDIVDS
Ch	VDCTL	MCU Voltage Domain Control	#PRCM_PRCM_REGISTERS_PRCM_ALL_VDCTL
28h	CLKLOADCTL	Load PRCM Settings To CLKCTRL Power Domain	#PRCM_PRCM_REGISTERS_PRCM_ALL_CLKLOADCTL
2Ch	RFCCLKG	RFC Clock Gate	#PRCM_PRCM_REGISTERS_PRCM_ALL_RFCCLKG
30h	VIMSCLKG	VIMS Clock Gate	#PRCM_PRCM_REGISTERS_PRCM_ALL_VIMSCLKG
3Ch	SECDMACLKGR	SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes	#PRCM_PRCM_REGISTERS_PRCM_ALL_SECDMACLKGR
40h	SECDMACLKGS	SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode	#PRCM_PRCM_REGISTERS_PRCM_ALL_SECDMACLKGS
44h	SECDMACLKGDS	SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode	#PRCM_PRCM_REGISTERS_PRCM_ALL_SECDMACLKGDS
48h	GPIOCLKGR	GPIO Clock Gate For Run And All Modes	#PRCM_PRCM_REGISTERS_PRCM_ALL_GPIOCLKGR
4Ch	GPIOCLKGS	GPIO Clock Gate For Sleep Mode	#PRCM_PRCM_REGISTERS_PRCM_ALL_GPIOCLKGS
50h	GPIOCLKGDS	GPIO Clock Gate For Deep Sleep Mode	#PRCM_PRCM_REGISTERS_PRCM_ALL_GPIOCLKGDS
54h	GPTCLKGR	GPT Clock Gate For Run And All Modes	#PRCM_PRCM_REGISTERS_PRCM_ALL_GPTCLKGR
58h	GPTCLKGS	GPT Clock Gate For Sleep Mode	#PRCM_PRCM_REGISTERS_PRCM_ALL_GPTCLKGS
5Ch	GPTCLKGDS	GPT Clock Gate For Deep Sleep Mode	#PRCM_PRCM_REGISTERS_PRCM_ALL_GPTCLKGDS
60h	I2CCLKGR	I2C Clock Gate For Run And All Modes	#PRCM_PRCM_REGISTERS_PRCM_ALL_I2CCLKGR
64h	I2CCLKGS	I2C Clock Gate For Sleep Mode	#PRCM_PRCM_REGISTERS_PRCM_ALL_I2CCLKGS
68h	I2CCLKGDS	I2C Clock Gate For Deep Sleep Mode	#PRCM_PRCM_REGISTERS_PRCM_ALL_I2CCLKGDS
6Ch	UARTCLKGR	UART Clock Gate For Run And All Modes	#PRCM_PRCM_REGISTERS_PRCM_ALL_UARTCLKGR
70h	UARTCLKGS	UART Clock Gate For Sleep Mode	#PRCM_PRCM_REGISTERS_PRCM_ALL_UARTCLKGS
74h	UARTCLKGDS	UART Clock Gate For Deep Sleep Mode	#PRCM_PRCM_REGISTERS_PRCM_ALL_UARTCLKGDS
78h	SSICLKGR	SSI Clock Gate For Run And All Modes	#PRCM_PRCM_REGISTERS_PRCM_ALL_SSICLKGR
7Ch	SSICLKGS	SSI Clock Gate For Sleep Mode	#PRCM_PRCM_REGISTERS_PRCM_ALL_SSICLKGS
80h	SSICLKGDS	SSI Clock Gate For Deep Sleep Mode	#PRCM_PRCM_REGISTERS_PRCM_ALL_SSICLKGDS
84h	I2SCLKGR	I2S Clock Gate For Run And All Modes	#PRCM_PRCM_REGISTERS_PRCM_ALL_I2SCLKGR
88h	I2SCLKGS	I2S Clock Gate For Sleep Mode	#PRCM_PRCM_REGISTERS_PRCM_ALL_I2SCLKGS
8Ch	I2SCLKGDS	I2S Clock Gate For Deep Sleep Mode	#PRCM_PRCM_REGISTERS_PRCM_ALL_I2SCLKGDS
B4h	SYSBUSCLKDIV	Internal	#PRCM_PRCM_REGISTERS_PRCM_ALL_SYSBUSCLKDIV
B8h	CPUCLKDIV	Internal	#PRCM_PRCM_REGISTERS_PRCM_ALL_CPUCLKDIV
BCh	PERBUSCPUCLKDIV	Internal	#PRCM_PRCM_REGISTERS_PRCM_ALL_PERBUSCPUCLKDIV
C4h	PERDMACLKDIV	Internal	#PRCM_PRCM_REGISTERS_PRCM_ALL_PERDMACLKDIV
C8h	I2SBCLKSEL	I2S Clock Control	#PRCM_PRCM_REGISTERS_PRCM_ALL_I2SBCLKSEL
CCh	GPTCLKDIV	GPT Scalar	#PRCM_PRCM_REGISTERS_PRCM_ALL_GPTCLKDIV
D0h	I2SCLKCTL	I2S Clock Control	#PRCM_PRCM_REGISTERS_PRCM_ALL_I2SCLKCTL
D4h	I2SMCLKDIV	MCLK Division Ratio	#PRCM_PRCM_REGISTERS_PRCM_ALL_I2SMCLKDIV
D8h	I2SBCLKDIV	BCLK Division Ratio	#PRCM_PRCM_REGISTERS_PRCM_ALL_I2SBCLKDIV
DCh	I2SWCLKDIV	WCLK Division Ratio	#PRCM_PRCM_REGISTERS_PRCM_ALL_I2SWCLKDIV
F0h	RESETSECDMA	RESET For SEC (PKA And TRNG And CRYPTO) And UDMA	#PRCM_PRCM_REGISTERS_PRCM_ALL_RESETSECDMA
F4h	RESETGPIO	RESET For GPIO IPs	#PRCM_PRCM_REGISTERS_PRCM_ALL_RESETGPIO
F8h	RESETGPT	RESET For GPT Ips	#PRCM_PRCM_REGISTERS_PRCM_ALL_RESETGPT
FCh	RESETI2C	RESET For I2C IPs	#PRCM_PRCM_REGISTERS_PRCM_ALL_RESETI2C
100h	RESETUART	RESET For UART IPs	#PRCM_PRCM_REGISTERS_PRCM_ALL_RESETUART
104h	RESETSSI	RESET For SSI IPs	#PRCM_PRCM_REGISTERS_PRCM_ALL_RESETSSI
108h	RESETI2S	RESET For I2S IP	#PRCM_PRCM_REGISTERS_PRCM_ALL_RESETI2S
12Ch	PDCTL0	Power Domain Control	#PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL0
130h	PDCTL0RFC	RFC Power Domain Control	#PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL0RFC
134h	PDCTL0SERIAL	SERIAL Power Domain Control	#PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL0SERIAL
138h	PDCTL0PERIPH	PERIPH Power Domain Control	#PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL0PERIPH
140h	PDSTAT0	Power Domain Status	#PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT0
144h	PDSTAT0RFC	RFC Power Domain Status	#PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT0RFC
148h	PDSTAT0SERIAL	SERIAL Power Domain Status	#PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT0SERIAL
14Ch	PDSTAT0PERIPH	PERIPH Power Domain Status	#PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT0PERIPH
17Ch	PDCTL1	Power Domain Control	#PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL1
184h	PDCTL1CPU	CPU Power Domain Direct Control	#PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL1CPU
188h	PDCTL1RFC	RFC Power Domain Direct Control	#PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL1RFC
18Ch	PDCTL1VIMS	VIMS Mode Direct Control	#PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL1VIMS
194h	PDSTAT1	Power Manager Status	#PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT1
198h	PDSTAT1BUS	BUS Power Domain Direct Read Status	#PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT1BUS
19Ch	PDSTAT1RFC	RFC Power Domain Direct Read Status	#PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT1RFC
1A0h	PDSTAT1CPU	CPU Power Domain Direct Read Status	#PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT1CPU
1A4h	PDSTAT1VIMS	VIMS Mode Direct Read Status	#PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT1VIMS
1CCh	RFCBITS	Control To RFC	#PRCM_PRCM_REGISTERS_PRCM_ALL_RFCBITS
1D0h	RFCMODESEL	Selected RFC Mode	#PRCM_PRCM_REGISTERS_PRCM_ALL_RFCMODESEL
1D4h	RFCMODEHWOPT	Allowed RFC Modes	#PRCM_PRCM_REGISTERS_PRCM_ALL_RFCMODEHWOPT
1E0h	PWRPROFSTAT	Power Profiler Register	#PRCM_PRCM_REGISTERS_PRCM_ALL_PWRPROFSTAT
224h	RAMRETEN	Memory Retention Control	#PRCM_PRCM_REGISTERS_PRCM_ALL_RAMRETEN
290h	OSCIMSC	Oscillator Interrupt Mask Control	#PRCM_PRCM_REGISTERS_PRCM_ALL_OSCIMSC
294h	OSCRIS	Oscillator Raw Interrupt Status	#PRCM_PRCM_REGISTERS_PRCM_ALL_OSCRIS
298h	OSCICR	Oscillator Raw Interrupt Clear	#PRCM_PRCM_REGISTERS_PRCM_ALL_OSCICR

Complex bit access types are encoded to fit into small table cells. #PRCM_PRCM_REGISTERS_LEGEND shows the codes that are used for access types in this section.

Table 8-28 PRCM Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

8.8.2.1 INFRCLKDIVR Register (Offset = 0h) [Reset = 00000000h]

INFRCLKDIVR is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_INFRCLKDIVR_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_INFRCLKDIVR_TABLE.

Return to the Summary Table.

Infrastructure Clock Division Factor For Run Mode

Figure 8-24 INFRCLKDIVR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														RATIO
R-0h														R/W-0h

Table 8-29 INFRCLKDIVR Register Field Descriptions

Bit

Field

Type

Reset

Description

31-2

RESERVED

Reserved

1-0

RATIO

R/W

Division rate for clocks driving modules in the MCU_AON domain when system CPU is in run mode. Division ratio affects both infrastructure clock and perbusull clock.

0h = Divide by 1

1h = Divide by 2

2h = Divide by 8

3h = Divide by 32

8.8.2.2 INFRCLKDIVS Register (Offset = 4h) [Reset = 00000000h]

INFRCLKDIVS is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_INFRCLKDIVS_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_INFRCLKDIVS_TABLE.

Return to the Summary Table.

Infrastructure Clock Division Factor For Sleep Mode

Figure 8-25 INFRCLKDIVS Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														RATIO
R-0h														R/W-0h

Table 8-30 INFRCLKDIVS Register Field Descriptions

Bit

Field

Type

Reset

Description

31-2

RESERVED

Reserved

1-0

RATIO

R/W

Division rate for clocks driving modules in the MCU_AON domain when system CPU is in sleep mode. Division ratio affects both infrastructure clock and perbusull clock.

0h = Divide by 1

1h = Divide by 2

2h = Divide by 8

3h = Divide by 32

8.8.2.3 INFRCLKDIVDS Register (Offset = 8h) [Reset = 00000000h]

INFRCLKDIVDS is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_INFRCLKDIVDS_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_INFRCLKDIVDS_TABLE.

Return to the Summary Table.

Infrastructure Clock Division Factor For DeepSleep Mode

Figure 8-26 INFRCLKDIVDS Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														RATIO
R-0h														R/W-0h

Table 8-31 INFRCLKDIVDS Register Field Descriptions

Bit

Field

Type

Reset

Description

31-2

RESERVED

Reserved

1-0

RATIO

R/W

Division rate for clocks driving modules in the MCU_AON domain when system CPU is in seepsleep mode. Division ratio affects both infrastructure clock and perbusull clock.

0h = Divide by 1

1h = Divide by 2

2h = Divide by 8

3h = Divide by 32

8.8.2.4 VDCTL Register (Offset = Ch) [Reset = 00000000h]

VDCTL is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_VDCTL_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_VDCTL_TABLE.

Return to the Summary Table.

MCU Voltage Domain Control

Figure 8-27 VDCTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							ULDO
R-0h							R/W-0h

Table 8-32 VDCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	ULDO	R/W	0h	Request PMCTL to switch to uLDO. 0: No request 1: Assert request when possible The bit will have no effect before the following requirements are met: 1. PDCTL1.CPU_ON = 0 2. PDCTL1.VIMS_MODE = x0 3. SECDMACLKGDS.DMA_CLK_EN = 0 and S.CRYPTO_CLK_EN] = 0 and SECDMACLKGR.DMA_AM_CLK_EN = 0 (Note: Settings must be loaded with CLKLOADCTL.LOAD) 4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 and SECDMACLKGR.CRYPTO_AM_CLK_EN = 0 (Note: Settings must be loaded with CLKLOADCTL.LOAD) 5. I2SCLKGDS.CLK_EN = 0 and I2SCLKGR.AM_CLK_EN = 0 (Note: Settings must be loaded with CLKLOADCTL.LOAD) 6. RFC do no request access to BUS 7. System CPU in deepsleep

8.8.2.5 CLKLOADCTL Register (Offset = 28h) [Reset = 00000002h]

CLKLOADCTL is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_CLKLOADCTL_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_CLKLOADCTL_TABLE.

Return to the Summary Table.

Load PRCM Settings To CLKCTRL Power Domain

Figure 8-28 CLKLOADCTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						LOAD_DONE	LOAD
R-0h						R-1h	W-0h

Table 8-33 CLKLOADCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1	LOAD_DONE	R	1h	Status of LOAD. Will be cleared to 0 when any of the registers requiring a LOAD is written to, and be set to 1 when a LOAD is done. Note that writing no change to a register will result in the LOAD_DONE being cleared. 0 : One or more registers have been write accessed after last LOAD 1 : No registers are write accessed after last LOAD
0	LOAD	W	0h	0: No action 1: Load settings to CLKCTRL. Bit is HW cleared. Multiple changes to settings may be done before LOAD is written once so all changes takes place at the same time. LOAD can also be done after single setting updates. Registers that needs to be followed by LOAD before settings being applied are: - SYSBUSCLKDIV - CPUCLKDIV - PERBUSCPUCLKDIV - PERDMACLKDIV - PERBUSCPUCLKG - RFCCLKG - VIMSCLKG - SECDMACLKGR - SECDMACLKGS - SECDMACLKGDS - GPIOCLKGR - GPIOCLKGS - GPIOCLKGDS - GPTCLKGR - GPTCLKGS - GPTCLKGDS - GPTCLKDIV - I2CCLKGR - I2CCLKGS - I2CCLKGDS - SSICLKGR - SSICLKGS - SSICLKGDS - UARTCLKGR - UARTCLKGS - UARTCLKGDS - I2SCLKGR - I2SCLKGS - I2SCLKGDS - I2SBCLKSEL - I2SCLKCTL - I2SMCLKDIV - I2SBCLKDIV - I2SWCLKDIV

8.8.2.6 RFCCLKG Register (Offset = 2Ch) [Reset = 00000001h]

RFCCLKG is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_RFCCLKG_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_RFCCLKG_TABLE.

Return to the Summary Table.

RFC Clock Gate

Figure 8-29 RFCCLKG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_EN
R-0h							R/W-1h

Table 8-34 RFCCLKG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	CLK_EN	R/W	1h	0: Disable Clock 1: Enable clock if RFC power domain is on For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.7 VIMSCLKG Register (Offset = 30h) [Reset = 00000003h]

VIMSCLKG is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_VIMSCLKG_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_VIMSCLKG_TABLE.

Return to the Summary Table.

VIMS Clock Gate

Figure 8-30 VIMSCLKG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														CLK_EN
R-0h														R/W-3h

Table 8-35 VIMSCLKG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1-0	CLK_EN	R/W	3h	00: Disable clock 01: Disable clock when SYSBUS clock is disabled 11: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.8 SECDMACLKGR Register (Offset = 3Ch) [Reset = 00000000h]

SECDMACLKGR is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_SECDMACLKGR_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_SECDMACLKGR_TABLE.

Return to the Summary Table.

SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes

Figure 8-31 SECDMACLKGR Register

31	30	29	28	27	26	25	24
RESERVED							DMA_AM_CLK_EN
R-0h							R/W-0h

23	22	21	20	19	18	17	16
RESERVED				PKA_ZERIOZE_RESET_N	PKA_AM_CLK_EN	TRNG_AM_CLK_EN	CRYPTO_AM_CLK_EN
R-0h				R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED							DMA_CLK_EN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED					PKA_CLK_EN	TRNG_CLK_EN	CRYPTO_CLK_EN
R-0h					R/W-0h	R/W-0h	R/W-0h

Table 8-36 SECDMACLKGR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24	DMA_AM_CLK_EN	R/W	0h	0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides DMA_CLK_EN, SECDMACLKGS.DMA_CLK_EN and SECDMACLKGDS.DMA_CLK_EN when enabled. SYSBUS clock will always run when enabled For changes to take effect, CLKLOADCTL.LOAD needs to be written
23-20	RESERVED	R	0h	Reserved
19	PKA_ZERIOZE_RESET_N	R/W	0h	Zeroization logic hardware reset. 0: pka_zeroize logic inactive. 1: pka_zeroize of memory is enabled. This register must remain active until the memory are completely zeroized which requires 256 periods on systembus clock.
18	PKA_AM_CLK_EN	R/W	0h	0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides PKA_CLK_EN, SECDMACLKGS.PKA_CLK_EN and SECDMACLKGDS.PKA_CLK_EN when enabled. For changes to take effect, CLKLOADCTL.LOAD needs to be written
17	TRNG_AM_CLK_EN	R/W	0h	0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides TRNG_CLK_EN, SECDMACLKGS.TRNG_CLK_EN and SECDMACLKGDS.TRNG_CLK_EN when enabled. For changes to take effect, CLKLOADCTL.LOAD needs to be written
16	CRYPTO_AM_CLK_EN	R/W	0h	0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CRYPTO_CLK_EN, SECDMACLKGS.CRYPTO_CLK_EN and SECDMACLKGDS.CRYPTO_CLK_EN when enabled. SYSBUS clock will always run when enabled For changes to take effect, CLKLOADCTL.LOAD needs to be written
15-9	RESERVED	R	0h	Reserved
8	DMA_CLK_EN	R/W	0h	0: Disable clock 1: Enable clock Can be forced on by DMA_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written
7-3	RESERVED	R	0h	Reserved
2	PKA_CLK_EN	R/W	0h	0: Disable clock 1: Enable clock Can be forced on by PKA_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written
1	TRNG_CLK_EN	R/W	0h	0: Disable clock 1: Enable clock Can be forced on by TRNG_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written
0	CRYPTO_CLK_EN	R/W	0h	0: Disable clock 1: Enable clock Can be forced on by CRYPTO_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.9 SECDMACLKGS Register (Offset = 40h) [Reset = 00000000h]

SECDMACLKGS is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_SECDMACLKGS_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_SECDMACLKGS_TABLE.

Return to the Summary Table.

SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode

Figure 8-32 SECDMACLKGS Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							DMA_CLK_EN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED					PKA_CLK_EN	TRNG_CLK_EN	CRYPTO_CLK_EN
R-0h					R/W-0h	R/W-0h	R/W-0h

Table 8-37 SECDMACLKGS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	DMA_CLK_EN	R/W	0h	0: Disable clock 1: Enable clock Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written
7-3	RESERVED	R	0h	Reserved
2	PKA_CLK_EN	R/W	0h	0: Disable clock 1: Enable clock Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written
1	TRNG_CLK_EN	R/W	0h	0: Disable clock 1: Enable clock Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written
0	CRYPTO_CLK_EN	R/W	0h	0: Disable clock 1: Enable clock Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.10 SECDMACLKGDS Register (Offset = 44h) [Reset = 00000000h]

SECDMACLKGDS is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_SECDMACLKGDS_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_SECDMACLKGDS_TABLE.

Return to the Summary Table.

SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode

Figure 8-33 SECDMACLKGDS Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							DMA_CLK_EN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED					PKA_CLK_EN	TRNG_CLK_EN	CRYPTO_CLK_EN
R-0h					R/W-0h	R/W-0h	R/W-0h

Table 8-38 SECDMACLKGDS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	DMA_CLK_EN	R/W	0h	0: Disable clock 1: Enable clock Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written
7-3	RESERVED	R	0h	Reserved
2	PKA_CLK_EN	R/W	0h	0: Disable clock 1: Enable clock Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written
1	TRNG_CLK_EN	R/W	0h	0: Disable clock 1: Enable clock SYSBUS clock will always run when enabled Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written
0	CRYPTO_CLK_EN	R/W	0h	0: Disable clock 1: Enable clock SYSBUS clock will always run when enabled Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.11 GPIOCLKGR Register (Offset = 48h) [Reset = 00000000h]

GPIOCLKGR is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_GPIOCLKGR_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_GPIOCLKGR_TABLE.

Return to the Summary Table.

GPIO Clock Gate For Run And All Modes

Figure 8-34 GPIOCLKGR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							AM_CLK_EN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_EN
R-0h							R/W-0h

Table 8-39 GPIOCLKGR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	AM_CLK_EN	R/W	0h	0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CLK_EN, GPIOCLKGS.CLK_EN and GPIOCLKGDS.CLK_EN when enabled. For changes to take effect, CLKLOADCTL.LOAD needs to be written
7-1	RESERVED	R	0h	Reserved
0	CLK_EN	R/W	0h	0: Disable clock 1: Enable clock Can be forced on by AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.12 GPIOCLKGS Register (Offset = 4Ch) [Reset = 00000000h]

GPIOCLKGS is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_GPIOCLKGS_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_GPIOCLKGS_TABLE.

Return to the Summary Table.

GPIO Clock Gate For Sleep Mode

Figure 8-35 GPIOCLKGS Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_EN
R-0h							R/W-0h

Table 8-40 GPIOCLKGS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	CLK_EN	R/W	0h	0: Disable clock 1: Enable clock Can be forced on by GPIOCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.13 GPIOCLKGDS Register (Offset = 50h) [Reset = 00000000h]

GPIOCLKGDS is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_GPIOCLKGDS_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_GPIOCLKGDS_TABLE.

Return to the Summary Table.

GPIO Clock Gate For Deep Sleep Mode

Figure 8-36 GPIOCLKGDS Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_EN
R-0h							R/W-0h

Table 8-41 GPIOCLKGDS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	CLK_EN	R/W	0h	0: Disable clock 1: Enable clock Can be forced on by GPIOCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.14 GPTCLKGR Register (Offset = 54h) [Reset = 00000000h]

GPTCLKGR is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_GPTCLKGR_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_GPTCLKGR_TABLE.

Return to the Summary Table.

GPT Clock Gate For Run And All Modes

Figure 8-37 GPTCLKGR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				AM_CLK_EN				RESERVED				CLK_EN
R-0h				R/W-0h				R-0h				R/W-0h

Table 8-42 GPTCLKGR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11-8	AM_CLK_EN	R/W	0h	Each bit below has the following meaning: 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CLK_EN, GPTCLKGS.CLK_EN and GPTCLKGDS.CLK_EN when enabled. ENUMs can be combined For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for GPT0 in all modes 2h = Enable clock for GPT1 in all modes 4h = Enable clock for GPT2 in all modes 8h = Enable clock for GPT3 in all modes
7-4	RESERVED	R	0h	Reserved
3-0	CLK_EN	R/W	0h	Each bit below has the following meaning: 0: Disable clock 1: Enable clock Can be forced on by AM_CLK_EN ENUMs can be combined For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for GPT0 2h = Enable clock for GPT1 4h = Enable clock for GPT2 8h = Enable clock for GPT3

8.8.2.15 GPTCLKGS Register (Offset = 58h) [Reset = 00000000h]

GPTCLKGS is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_GPTCLKGS_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_GPTCLKGS_TABLE.

Return to the Summary Table.

GPT Clock Gate For Sleep Mode

Figure 8-38 GPTCLKGS Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												CLK_EN
R-0h												R/W-0h

Table 8-43 GPTCLKGS Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

Reserved

3-0

CLK_EN

R/W

Each bit below has the following meaning:
0: Disable clock
1: Enable clock
Can be forced on by GPTCLKGR.AM_CLK_EN
ENUMs can be combined
For changes to take effect, CLKLOADCTL.LOAD needs to be written

1h = Enable clock for GPT0

2h = Enable clock for GPT1

4h = Enable clock for GPT2

8h = Enable clock for GPT3

8.8.2.16 GPTCLKGDS Register (Offset = 5Ch) [Reset = 00000000h]

GPTCLKGDS is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_GPTCLKGDS_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_GPTCLKGDS_TABLE.

Return to the Summary Table.

GPT Clock Gate For Deep Sleep Mode

Figure 8-39 GPTCLKGDS Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												CLK_EN
R-0h												R/W-0h

Table 8-44 GPTCLKGDS Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

Reserved

3-0

CLK_EN

R/W

Each bit below has the following meaning:
0: Disable clock
1: Enable clock
Can be forced on by GPTCLKGR.AM_CLK_EN
ENUMs can be combined
For changes to take effect, CLKLOADCTL.LOAD needs to be written

1h = Enable clock for GPT0

2h = Enable clock for GPT1

4h = Enable clock for GPT2

8h = Enable clock for GPT3

8.8.2.17 I2CCLKGR Register (Offset = 60h) [Reset = 00000000h]

I2CCLKGR is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2CCLKGR_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2CCLKGR_TABLE.

Return to the Summary Table.

I2C Clock Gate For Run And All Modes

Figure 8-40 I2CCLKGR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							AM_CLK_EN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_EN
R-0h							R/W-0h

Table 8-45 I2CCLKGR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	AM_CLK_EN	R/W	0h	0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CLK_EN, I2CCLKGS.CLK_EN and I2CCLKGDS.CLK_EN when enabled. For changes to take effect, CLKLOADCTL.LOAD needs to be written
7-1	RESERVED	R	0h	Reserved
0	CLK_EN	R/W	0h	0: Disable clock 1: Enable clock Can be forced on by AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.18 I2CCLKGS Register (Offset = 64h) [Reset = 00000000h]

I2CCLKGS is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2CCLKGS_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2CCLKGS_TABLE.

Return to the Summary Table.

I2C Clock Gate For Sleep Mode

Figure 8-41 I2CCLKGS Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_EN
R-0h							R/W-0h

Table 8-46 I2CCLKGS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	CLK_EN	R/W	0h	0: Disable clock 1: Enable clock Can be forced on by I2CCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.19 I2CCLKGDS Register (Offset = 68h) [Reset = 00000000h]

I2CCLKGDS is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2CCLKGDS_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2CCLKGDS_TABLE.

Return to the Summary Table.

I2C Clock Gate For Deep Sleep Mode

Figure 8-42 I2CCLKGDS Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_EN
R-0h							R/W-0h

Table 8-47 I2CCLKGDS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	CLK_EN	R/W	0h	0: Disable clock 1: Enable clock Can be forced on by I2CCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.20 UARTCLKGR Register (Offset = 6Ch) [Reset = 00000000h]

UARTCLKGR is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_UARTCLKGR_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_UARTCLKGR_TABLE.

Return to the Summary Table.

UART Clock Gate For Run And All Modes

Figure 8-43 UARTCLKGR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED						AM_CLK_EN
R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED						CLK_EN
R-0h						R/W-0h

Table 8-48 UARTCLKGR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	RESERVED	R	0h	Reserved
9-8	AM_CLK_EN	R/W	0h	0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CLK_EN, UARTCLKGS.CLK_EN and UARTCLKGDS.CLK_EN when enabled. For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for UART0 2h = Enable clock for UART1
7-2	RESERVED	R	0h	Reserved
1-0	CLK_EN	R/W	0h	0: Disable clock 1: Enable clock Can be forced on by AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for UART0 2h = Enable clock for UART1

8.8.2.21 UARTCLKGS Register (Offset = 70h) [Reset = 00000000h]

UARTCLKGS is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_UARTCLKGS_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_UARTCLKGS_TABLE.

Return to the Summary Table.

UART Clock Gate For Sleep Mode

Figure 8-44 UARTCLKGS Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														CLK_EN
R-0h														R/W-0h

Table 8-49 UARTCLKGS Register Field Descriptions

Bit

Field

Type

Reset

Description

31-2

RESERVED

Reserved

1-0

CLK_EN

R/W

0: Disable clock
1: Enable clock
Can be forced on by UARTCLKGR.AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written

1h = Enable clock for UART0

2h = Enable clock for UART1

8.8.2.22 UARTCLKGDS Register (Offset = 74h) [Reset = 00000000h]

UARTCLKGDS is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_UARTCLKGDS_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_UARTCLKGDS_TABLE.

Return to the Summary Table.

UART Clock Gate For Deep Sleep Mode

Figure 8-45 UARTCLKGDS Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														CLK_EN
R-0h														R/W-0h

Table 8-50 UARTCLKGDS Register Field Descriptions

Bit

Field

Type

Reset

Description

31-2

RESERVED

Reserved

1-0

CLK_EN

R/W

0: Disable clock
1: Enable clock
Can be forced on by UARTCLKGR.AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written

1h = Enable clock for UART0

2h = Enable clock for UART1

8.8.2.23 SSICLKGR Register (Offset = 78h) [Reset = 00000000h]

SSICLKGR is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_SSICLKGR_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_SSICLKGR_TABLE.

Return to the Summary Table.

SSI Clock Gate For Run And All Modes

Figure 8-46 SSICLKGR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED						AM_CLK_EN
R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED						CLK_EN
R-0h						R/W-0h

Table 8-51 SSICLKGR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	RESERVED	R	0h	Reserved
9-8	AM_CLK_EN	R/W	0h	0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CLK_EN, SSICLKGS.CLK_EN and SSICLKGDS.CLK_EN when enabled. For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for SSI0 2h = Enable clock for SSI1
7-2	RESERVED	R	0h	Reserved
1-0	CLK_EN	R/W	0h	0: Disable clock 1: Enable clock Can be forced on by AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for SSI0 2h = Enable clock for SSI1

8.8.2.24 SSICLKGS Register (Offset = 7Ch) [Reset = 00000000h]

SSICLKGS is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_SSICLKGS_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_SSICLKGS_TABLE.

Return to the Summary Table.

SSI Clock Gate For Sleep Mode

Figure 8-47 SSICLKGS Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														CLK_EN
R-0h														R/W-0h

Table 8-52 SSICLKGS Register Field Descriptions

Bit

Field

Type

Reset

Description

31-2

RESERVED

Reserved

1-0

CLK_EN

R/W

0: Disable clock
1: Enable clock
Can be forced on by SSICLKGR.AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written

1h = Enable clock for SSI0

2h = Enable clock for SSI1

8.8.2.25 SSICLKGDS Register (Offset = 80h) [Reset = 00000000h]

SSICLKGDS is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_SSICLKGDS_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_SSICLKGDS_TABLE.

Return to the Summary Table.

SSI Clock Gate For Deep Sleep Mode

Figure 8-48 SSICLKGDS Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														CLK_EN
R-0h														R/W-0h

Table 8-53 SSICLKGDS Register Field Descriptions

Bit

Field

Type

Reset

Description

31-2

RESERVED

Reserved

1-0

CLK_EN

R/W

0: Disable clock
1: Enable clock
Can be forced on by SSICLKGR.AM_CLK_EN
For changes to take effect, CLKLOADCTL.LOAD needs to be written

1h = Enable clock for SSI0

2h = Enable clock for SSI1

8.8.2.26 I2SCLKGR Register (Offset = 84h) [Reset = 00000000h]

I2SCLKGR is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2SCLKGR_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2SCLKGR_TABLE.

Return to the Summary Table.

I2S Clock Gate For Run And All Modes

Figure 8-49 I2SCLKGR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							AM_CLK_EN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_EN
R-0h							R/W-0h

Table 8-54 I2SCLKGR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	AM_CLK_EN	R/W	0h	0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CLK_EN, I2SCLKGS.CLK_EN and I2SCLKGDS.CLK_EN when enabled. SYSBUS clock will always run when enabled For changes to take effect, CLKLOADCTL.LOAD needs to be written
7-1	RESERVED	R	0h	Reserved
0	CLK_EN	R/W	0h	0: Disable clock 1: Enable clock Can be forced on by AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.27 I2SCLKGS Register (Offset = 88h) [Reset = 00000000h]

I2SCLKGS is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2SCLKGS_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2SCLKGS_TABLE.

Return to the Summary Table.

I2S Clock Gate For Sleep Mode

Figure 8-50 I2SCLKGS Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_EN
R-0h							R/W-0h

Table 8-55 I2SCLKGS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	CLK_EN	R/W	0h	0: Disable clock 1: Enable clock Can be forced on by I2SCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.28 I2SCLKGDS Register (Offset = 8Ch) [Reset = 00000000h]

I2SCLKGDS is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2SCLKGDS_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2SCLKGDS_TABLE.

Return to the Summary Table.

I2S Clock Gate For Deep Sleep Mode

Figure 8-51 I2SCLKGDS Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_EN
R-0h							R/W-0h

Table 8-56 I2SCLKGDS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	CLK_EN	R/W	0h	0: Disable clock 1: Enable clock SYSBUS clock will always run when enabled Can be forced on by I2SCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.29 SYSBUSCLKDIV Register (Offset = B4h) [Reset = 00000000h]

SYSBUSCLKDIV is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_SYSBUSCLKDIV_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_SYSBUSCLKDIV_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 8-52 SYSBUSCLKDIV Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													RATIO
R-0h													R/W-0h

Table 8-57 SYSBUSCLKDIV Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2-0	RATIO	R/W	0h	Internal. Only to be used through TI provided API.

8.8.2.30 CPUCLKDIV Register (Offset = B8h) [Reset = 00000000h]

CPUCLKDIV is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_CPUCLKDIV_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_CPUCLKDIV_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 8-53 CPUCLKDIV Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							RATIO
R-0h							R/W-0h

Table 8-58 CPUCLKDIV Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	RATIO	R/W	0h	Internal. Only to be used through TI provided API.

8.8.2.31 PERBUSCPUCLKDIV Register (Offset = BCh) [Reset = 00000000h]

PERBUSCPUCLKDIV is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_PERBUSCPUCLKDIV_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_PERBUSCPUCLKDIV_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 8-54 PERBUSCPUCLKDIV Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												RATIO
R-0h												R/W-0h

Table 8-59 PERBUSCPUCLKDIV Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3-0	RATIO	R/W	0h	Internal. Only to be used through TI provided API.

8.8.2.32 PERDMACLKDIV Register (Offset = C4h) [Reset = 00000000h]

PERDMACLKDIV is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_PERDMACLKDIV_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_PERDMACLKDIV_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 8-55 PERDMACLKDIV Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												RATIO
R-0h												R/W-0h

Table 8-60 PERDMACLKDIV Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3-0	RATIO	R/W	0h	Internal. Only to be used through TI provided API.

8.8.2.33 I2SBCLKSEL Register (Offset = C8h) [Reset = 00000000h]

I2SBCLKSEL is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2SBCLKSEL_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2SBCLKSEL_TABLE.

Return to the Summary Table.

I2S Clock Control

Figure 8-56 I2SBCLKSEL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															SRC
R-0h															R/W-0h

Table 8-61 I2SBCLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	SRC	R/W	0h	BCLK source selector 0: Use external BCLK 1: Use internally generated clock For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.34 GPTCLKDIV Register (Offset = CCh) [Reset = 00000000h]

GPTCLKDIV is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_GPTCLKDIV_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_GPTCLKDIV_TABLE.

Return to the Summary Table.

GPT Scalar

Figure 8-57 GPTCLKDIV Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												RATIO
R-0h												R/W-0h

Table 8-62 GPTCLKDIV Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

Reserved

3-0

RATIO

R/W

Scalar used for GPTs. The division rate will be constant and ungated for Run / Sleep / DeepSleep mode. For changes to take effect, CLKLOADCTL.LOAD needs to be written Other values are not supported.

0h = Divide by 1

1h = Divide by 2

2h = Divide by 4

3h = Divide by 8

4h = Divide by 16

5h = Divide by 32

6h = Divide by 64

7h = Divide by 128

8h = Divide by 256

8.8.2.35 I2SCLKCTL Register (Offset = D0h) [Reset = 00000000h]

I2SCLKCTL is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2SCLKCTL_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2SCLKCTL_TABLE.

Return to the Summary Table.

I2S Clock Control

Figure 8-58 I2SCLKCTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				SMPL_ON_POSEDGE	WCLK_PHASE		EN
R-0h				R/W-0h	R/W-0h		R/W-0h

Table 8-63 I2SCLKCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3	SMPL_ON_POSEDGE	R/W	0h	On the I2S serial interface, data and WCLK is sampled and clocked out on opposite edges of BCLK. 0 - data and WCLK are sampled on the negative edge and clocked out on the positive edge. 1 - data and WCLK are sampled on the positive edge and clocked out on the negative edge. For changes to take effect, CLKLOADCTL.LOAD needs to be written
2-1	WCLK_PHASE	R/W	0h	Decides how the WCLK division ratio is calculated and used to generate different duty cycles (See I2SWCLKDIV.WDIV). 0: Single phase 1: Dual phase 2: User Defined 3: Reserved/Undefined For changes to take effect, CLKLOADCTL.LOAD needs to be written
0	EN	R/W	0h	0: MCLK, BCLK and WCLK will be static low 1: Enables the generation of MCLK, BCLK and WCLK For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.36 I2SMCLKDIV Register (Offset = D4h) [Reset = 00000000h]

I2SMCLKDIV is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2SMCLKDIV_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2SMCLKDIV_TABLE.

Return to the Summary Table.

MCLK Division Ratio

Figure 8-59 I2SMCLKDIV Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																						MDIV
R-0h																						R/W-0h

Table 8-64 I2SMCLKDIV Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	RESERVED	R	0h	Reserved
9-0	MDIV	R/W	0h	An unsigned factor of the division ratio used to generate MCLK [2-1024]: MCLK = MCUCLK/MDIV[Hz] MCUCLK is 48MHz. A value of 0 is interpreted as 1024. A value of 1 is invalid. If MDIV is odd the low phase of the clock is one MCUCLK period longer than the high phase. For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.37 I2SBCLKDIV Register (Offset = D8h) [Reset = 00000000h]

I2SBCLKDIV is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2SBCLKDIV_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2SBCLKDIV_TABLE.

Return to the Summary Table.

BCLK Division Ratio

Figure 8-60 I2SBCLKDIV Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																						BDIV
R-0h																						R/W-0h

Table 8-65 I2SBCLKDIV Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	RESERVED	R	0h	Reserved
9-0	BDIV	R/W	0h	An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]: BCLK = MCUCLK/BDIV[Hz] MCUCLK is 48MHz. A value of 0 is interpreted as 1024. A value of 1 is invalid. If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0, the low phase of the clock is one MCUCLK period longer than the high phase. If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 1 , the high phase of the clock is one MCUCLK period longer than the low phase. For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.38 I2SWCLKDIV Register (Offset = DCh) [Reset = 00000000h]

I2SWCLKDIV is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2SWCLKDIV_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_I2SWCLKDIV_TABLE.

Return to the Summary Table.

WCLK Division Ratio

Figure 8-61 I2SWCLKDIV Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																WDIV
R-0h																R/W-0h

Table 8-66 I2SWCLKDIV Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	WDIV	R/W	0h	If I2SCLKCTL.WCLK_PHASE = 0, Single phase. WCLK is high one BCLK period and low WDIV[9:0] (unsigned, [1-1023]) BCLK periods. WCLK = MCUCLK / BDIV(WDIV[9:0] + 1) [Hz] MCUCLK is 48MHz. If I2SCLKCTL.WCLK_PHASE = 1, Dual phase. Each phase on WCLK (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) BCLK periods. WCLK = MCUCLK / BDIV(2WDIV[9:0]) [Hz] If I2SCLKCTL.WCLK_PHASE = 2, User defined. WCLK is high WDIV[7:0] (unsigned, [1-255]) BCLK periods and low WDIV[15:8] (unsigned, [1-255]) BCLK periods. WCLK = MCUCLK / (BDIV(WDIV[7:0] + WDIV[15:8]) [Hz] For changes to take effect, CLKLOADCTL.LOAD needs to be written

8.8.2.39 RESETSECDMA Register (Offset = F0h) [Reset = 00000000h]

RESETSECDMA is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_RESETSECDMA_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_RESETSECDMA_TABLE.

Return to the Summary Table.

RESET For SEC (PKA And TRNG And CRYPTO) And UDMA

Figure 8-62 RESETSECDMA Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							DMA
R-0h							W-0h

7	6	5	4	3	2	1	0
RESERVED					PKA	TRNG	CRYPTO
R-0h					W-0h	W-0h	W-0h

Table 8-67 RESETSECDMA Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	DMA	W	0h	Write 1 to reset. HW cleared. Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.
7-3	RESERVED	R	0h	Reserved
2	PKA	W	0h	Write 1 to reset. HW cleared. Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.
1	TRNG	W	0h	Write 1 to reset. HW cleared. Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.
0	CRYPTO	W	0h	Write 1 to reset. HW cleared. Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

8.8.2.40 RESETGPIO Register (Offset = F4h) [Reset = 00000000h]

RESETGPIO is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_RESETGPIO_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_RESETGPIO_TABLE.

Return to the Summary Table.

RESET For GPIO IPs

Figure 8-63 RESETGPIO Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							GPIO
R-0h							W-0h

Table 8-68 RESETGPIO Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	GPIO	W	0h	0: No action 1: Reset GPIO. HW cleared. Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

8.8.2.41 RESETGPT Register (Offset = F8h) [Reset = 00000000h]

RESETGPT is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_RESETGPT_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_RESETGPT_TABLE.

Return to the Summary Table.

RESET For GPT Ips

Figure 8-64 RESETGPT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															GPT
R-0h															W-0h

Table 8-69 RESETGPT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	GPT	W	0h	0: No action 1: Reset all GPTs. HW cleared. Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

8.8.2.42 RESETI2C Register (Offset = FCh) [Reset = 00000000h]

RESETI2C is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_RESETI2C_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_RESETI2C_TABLE.

Return to the Summary Table.

RESET For I2C IPs

Figure 8-65 RESETI2C Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															I2C
R-0h															W-0h

Table 8-70 RESETI2C Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	I2C	W	0h	0: No action 1: Reset I2C. HW cleared. Acess will only have effect when SERIAL power domain is on, PDSTAT0.SERIAL_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

8.8.2.43 RESETUART Register (Offset = 100h) [Reset = 00000000h]

RESETUART is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_RESETUART_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_RESETUART_TABLE.

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RESET For UART IPs

Figure 8-66 RESETUART Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						UART1	UART0
R-0h						W-0h	W-0h

Table 8-71 RESETUART Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1	UART1	W	0h	0: No action 1: Reset UART1. HW cleared. Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.
0	UART0	W	0h	0: No action 1: Reset UART0. HW cleared. Acess will only have effect when SERIAL power domain is on, PDSTAT0.SERIAL_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

8.8.2.44 RESETSSI Register (Offset = 104h) [Reset = 00000000h]

RESETSSI is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_RESETSSI_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_RESETSSI_TABLE.

Return to the Summary Table.

RESET For SSI IPs

Figure 8-67 RESETSSI Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														SSI
R-0h														W-0h

Table 8-72 RESETSSI Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1-0	SSI	W	0h	SSI 0: 0: No action 1: Reset SSI. HW cleared. Acess will only have effect when SERIAL power domain is on, PDSTAT0.SERIAL_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. SSI 1: 0: No action 1: Reset SSI. HW cleared. Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

8.8.2.45 RESETI2S Register (Offset = 108h) [Reset = 00000000h]

RESETI2S is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_RESETI2S_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_RESETI2S_TABLE.

Return to the Summary Table.

RESET For I2S IP

Figure 8-68 RESETI2S Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															I2S
R-0h															W-0h

Table 8-73 RESETI2S Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	I2S	W	0h	0: No action 1: Reset module. HW cleared. Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

8.8.2.46 PDCTL0 Register (Offset = 12Ch) [Reset = 00000000h]

PDCTL0 is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL0_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL0_TABLE.

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Power Domain Control

Figure 8-69 PDCTL0 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					PERIPH_ON	SERIAL_ON	RFC_ON
R-0h					R/W-0h	R/W-0h	R/W-0h

Table 8-74 PDCTL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	PERIPH_ON	R/W	0h	PERIPH Power domain. 0: PERIPH power domain is powered down 1: PERIPH power domain is powered up
1	SERIAL_ON	R/W	0h	SERIAL Power domain. 0: SERIAL power domain is powered down 1: SERIAL power domain is powered up
0	RFC_ON	R/W	0h	0: RFC power domain powered off if also PDCTL1.RFC_ON = 0 1: RFC power domain powered on

8.8.2.47 PDCTL0RFC Register (Offset = 130h) [Reset = 00000000h]

PDCTL0RFC is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL0RFC_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL0RFC_TABLE.

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RFC Power Domain Control

Figure 8-70 PDCTL0RFC Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															ON
R-0h															R/W-0h

Table 8-75 PDCTL0RFC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	ON	R/W	0h	Alias for PDCTL0.RFC_ON

8.8.2.48 PDCTL0SERIAL Register (Offset = 134h) [Reset = 00000000h]

PDCTL0SERIAL is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL0SERIAL_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL0SERIAL_TABLE.

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SERIAL Power Domain Control

Figure 8-71 PDCTL0SERIAL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															ON
R-0h															R/W-0h

Table 8-76 PDCTL0SERIAL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	ON	R/W	0h	Alias for PDCTL0.SERIAL_ON

8.8.2.49 PDCTL0PERIPH Register (Offset = 138h) [Reset = 00000000h]

PDCTL0PERIPH is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL0PERIPH_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL0PERIPH_TABLE.

Return to the Summary Table.

PERIPH Power Domain Control

Figure 8-72 PDCTL0PERIPH Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															ON
R-0h															R/W-0h

Table 8-77 PDCTL0PERIPH Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	ON	R/W	0h	Alias for PDCTL0.PERIPH_ON

8.8.2.50 PDSTAT0 Register (Offset = 140h) [Reset = 00000000h]

PDSTAT0 is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT0_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT0_TABLE.

Return to the Summary Table.

Power Domain Status

Figure 8-73 PDSTAT0 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					PERIPH_ON	SERIAL_ON	RFC_ON
R-0h					R-0h	R-0h	R-0h

Table 8-78 PDSTAT0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	PERIPH_ON	R	0h	PERIPH Power domain. 0: Domain may be powered down 1: Domain powered up (guaranteed)
1	SERIAL_ON	R	0h	SERIAL Power domain. 0: Domain may be powered down 1: Domain powered up (guaranteed)
0	RFC_ON	R	0h	RFC Power domain 0: Domain may be powered down 1: Domain powered up (guaranteed)

8.8.2.51 PDSTAT0RFC Register (Offset = 144h) [Reset = 00000000h]

PDSTAT0RFC is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT0RFC_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT0RFC_TABLE.

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RFC Power Domain Status

Figure 8-74 PDSTAT0RFC Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															ON
R-0h															R-0h

Table 8-79 PDSTAT0RFC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	ON	R	0h	Alias for PDSTAT0.RFC_ON

8.8.2.52 PDSTAT0SERIAL Register (Offset = 148h) [Reset = 00000000h]

PDSTAT0SERIAL is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT0SERIAL_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT0SERIAL_TABLE.

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SERIAL Power Domain Status

Figure 8-75 PDSTAT0SERIAL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															ON
R-0h															R-0h

Table 8-80 PDSTAT0SERIAL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	ON	R	0h	Alias for PDSTAT0.SERIAL_ON

8.8.2.53 PDSTAT0PERIPH Register (Offset = 14Ch) [Reset = 00000000h]

PDSTAT0PERIPH is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT0PERIPH_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT0PERIPH_TABLE.

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PERIPH Power Domain Status

Figure 8-76 PDSTAT0PERIPH Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															ON
R-0h															R-0h

Table 8-81 PDSTAT0PERIPH Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	ON	R	0h	Alias for PDSTAT0.PERIPH_ON

8.8.2.54 PDCTL1 Register (Offset = 17Ch) [Reset = 0000000Ah]

PDCTL1 is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL1_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL1_TABLE.

Return to the Summary Table.

Power Domain Control

Figure 8-77 PDCTL1 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			VIMS_MODE		RFC_ON	CPU_ON	RESERVED
R-0h			R/W-1h		R/W-0h	R/W-1h	R-0h

Table 8-82 PDCTL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4-3	VIMS_MODE	R/W	1h	00: VIMS power domain is only powered when CPU power domain is powered. 01: VIMS power domain is powered whenever the BUS power domain is powered. 1X: Block power up of VIMS power domain at next wake up. This mode only has effect when VIMS power domain is not powered. Used for Autonomous RF Core.
2	RFC_ON	R/W	0h	0: RFC power domain powered off if also PDCTL0.RFC_ON = 0 1: RFC power domain powered on Bit shall be used by RFC in autonomous mode but there is no HW restrictions fom system CPU to access the bit.
1	CPU_ON	R/W	1h	0: Causes a power down of the CPU power domain when system CPU indicates it is idle. 1: Initiates power-on of the CPU power domain. This bit is automatically set by a WIC power-on event.
0	RESERVED	R	0h	Reserved

8.8.2.55 PDCTL1CPU Register (Offset = 184h) [Reset = 00000001h]

PDCTL1CPU is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL1CPU_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL1CPU_TABLE.

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CPU Power Domain Direct Control

Figure 8-78 PDCTL1CPU Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															ON
R-0h															R/W-1h

Table 8-83 PDCTL1CPU Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	ON	R/W	1h	This is an alias for PDCTL1.CPU_ON

8.8.2.56 PDCTL1RFC Register (Offset = 188h) [Reset = 00000000h]

PDCTL1RFC is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL1RFC_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL1RFC_TABLE.

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RFC Power Domain Direct Control

Figure 8-79 PDCTL1RFC Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															ON
R-0h															R/W-0h

Table 8-84 PDCTL1RFC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	ON	R/W	0h	This is an alias for PDCTL1.RFC_ON

8.8.2.57 PDCTL1VIMS Register (Offset = 18Ch) [Reset = 00000001h]

PDCTL1VIMS is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL1VIMS_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDCTL1VIMS_TABLE.

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VIMS Mode Direct Control

Figure 8-80 PDCTL1VIMS Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														MODE
R-0h														R/W-1h

Table 8-85 PDCTL1VIMS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1-0	MODE	R/W	1h	This is an alias for PDCTL1.VIMS_MODE

8.8.2.58 PDSTAT1 Register (Offset = 194h) [Reset = 0000001Ah]

PDSTAT1 is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT1_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT1_TABLE.

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Power Manager Status

Figure 8-81 PDSTAT1 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			BUS_ON	VIMS_ON	RFC_ON	CPU_ON	RESERVED
R-0h			R-1h	R-1h	R-0h	R-1h	R-0h

Table 8-86 PDSTAT1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4	BUS_ON	R	1h	0: BUS domain not accessible 1: BUS domain is currently accessible
3	VIMS_ON	R	1h	0: VIMS domain not accessible 1: VIMS domain is currently accessible
2	RFC_ON	R	0h	0: RFC domain not accessible 1: RFC domain is currently accessible
1	CPU_ON	R	1h	0: CPU and BUS domain not accessible 1: CPU and BUS domains are both currently accessible
0	RESERVED	R	0h	Reserved

8.8.2.59 PDSTAT1BUS Register (Offset = 198h) [Reset = 00000001h]

PDSTAT1BUS is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT1BUS_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT1BUS_TABLE.

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BUS Power Domain Direct Read Status

Figure 8-82 PDSTAT1BUS Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															ON
R-0h															R-1h

Table 8-87 PDSTAT1BUS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	ON	R	1h	This is an alias for PDSTAT1.BUS_ON

8.8.2.60 PDSTAT1RFC Register (Offset = 19Ch) [Reset = 00000000h]

PDSTAT1RFC is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT1RFC_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT1RFC_TABLE.

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RFC Power Domain Direct Read Status

Figure 8-83 PDSTAT1RFC Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															ON
R-0h															R-0h

Table 8-88 PDSTAT1RFC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	ON	R	0h	This is an alias for PDSTAT1.RFC_ON

8.8.2.61 PDSTAT1CPU Register (Offset = 1A0h) [Reset = 00000001h]

PDSTAT1CPU is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT1CPU_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT1CPU_TABLE.

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CPU Power Domain Direct Read Status

Figure 8-84 PDSTAT1CPU Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															ON
R-0h															R-1h

Table 8-89 PDSTAT1CPU Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	ON	R	1h	This is an alias for PDSTAT1.CPU_ON

8.8.2.62 PDSTAT1VIMS Register (Offset = 1A4h) [Reset = 00000001h]

PDSTAT1VIMS is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT1VIMS_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_PDSTAT1VIMS_TABLE.

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VIMS Mode Direct Read Status

Figure 8-85 PDSTAT1VIMS Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															ON
R-0h															R-1h

Table 8-90 PDSTAT1VIMS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	ON	R	1h	This is an alias for PDSTAT1.VIMS_ON

8.8.2.63 RFCBITS Register (Offset = 1CCh) [Reset = 00000000h]

RFCBITS is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_RFCBITS_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_RFCBITS_TABLE.

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Control To RFC

Figure 8-86 RFCBITS Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
READ
R/W-0h

Table 8-91 RFCBITS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	READ	R/W	0h	Control bits for RFC. The RF core CPE processor will automatically check this register when it boots, and it can be used to immediately instruct CPE to perform some tasks at its start-up. The supported functionality is ROM-defined and may vary. See the technical reference manual for more details.

8.8.2.64 RFCMODESEL Register (Offset = 1D0h) [Reset = 00000000h]

RFCMODESEL is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_RFCMODESEL_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_RFCMODESEL_TABLE.

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Selected RFC Mode

Figure 8-87 RFCMODESEL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													CURR
R-0h													R/W-0h

Table 8-92 RFCMODESEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-3

RESERVED

Reserved

2-0

CURR

R/W

Selects the set of commands that the RFC will accept. Only modes permitted by RFCMODEHWOPT.AVAIL are writeable. See the technical reference manual for details.

0h = Select Mode 0

1h = Select Mode 1

2h = Select Mode 2

3h = Select Mode 3

4h = Select Mode 4

5h = Select Mode 5

6h = Select Mode 6

7h = Select Mode 7

8.8.2.65 RFCMODEHWOPT Register (Offset = 1D4h) [Reset = 00000000h]

RFCMODEHWOPT is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_RFCMODEHWOPT_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_RFCMODEHWOPT_TABLE.

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Allowed RFC Modes

Figure 8-88 RFCMODEHWOPT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								AVAIL
R-0h																								R-0h

Table 8-93 RFCMODEHWOPT Register Field Descriptions

Bit

Field

Type

Reset

Description

31-8

RESERVED

Reserved

7-0

AVAIL

Permitted RFC modes. More than one mode can be permitted.

1h = Mode 0 permitted

2h = Mode 1 permitted

4h = Mode 2 permitted

8h = Mode 3 permitted

10h = Mode 4 permitted

20h = Mode 5 permitted

40h = Mode 6 permitted

80h = Mode 7 permitted

8.8.2.66 PWRPROFSTAT Register (Offset = 1E0h) [Reset = 00000001h]

PWRPROFSTAT is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_PWRPROFSTAT_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_PWRPROFSTAT_TABLE.

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Power Profiler Register

Figure 8-89 PWRPROFSTAT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								VALUE
R-0h																								R/W-1h

Table 8-94 PWRPROFSTAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	VALUE	R/W	1h	SW can use these bits to timestamp the application. These bits are also available through the testtap and can thus be used by the emulator to profile in real time.

8.8.2.67 RAMRETEN Register (Offset = 224h) [Reset = 0000000Bh]

RAMRETEN is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_RAMRETEN_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_RAMRETEN_TABLE.

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Memory Retention Control

Figure 8-90 RAMRETEN Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				RFCULL	RFC	VIMS
R-0h				R/W-1h	R/W-0h	R/W-3h

Table 8-95 RAMRETEN Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3	RFCULL	R/W	1h	0: Retention for RFC ULL SRAM disabled 1: Retention for RFC ULL SRAM enabled Memories controlled: CPEULLRAM
2	RFC	R/W	0h	0: Retention for RFC SRAM disabled 1: Retention for RFC SRAM enabled Memories controlled: CPERAM MCERAM RFERAM DSBRAM
1-0	VIMS	R/W	3h	0: Memory retention disabled 1: Memory retention enabled Bit 0: VIMS_TRAM Bit 1: VIMS_CRAM Legal modes depend on settings in VIMS:CTL.MODE 00: VIMS:CTL.MODE must be OFF before DEEPSLEEP is asserted - must be set to CACHE or SPLIT mode after waking up again 01: VIMS:CTL.MODE must be GPRAM before DEEPSLEEP is asserted. Must remain in GPRAM mode after wake up, alternatively select OFF mode first and then CACHE or SPILT mode. 10: Illegal mode 11: No restrictions

8.8.2.68 OSCIMSC Register (Offset = 290h) [Reset = 00000036h]

OSCIMSC is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_OSCIMSC_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_OSCIMSC_TABLE.

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Oscillator Interrupt Mask Control

Figure 8-91 OSCIMSC Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
HFSRCPENDIM	LFSRCDONEIM	XOSCDLFIM	XOSCLFIM	RCOSCDLFIM	RCOSCLFIM	XOSCHFIM	RCOSCHFIM
R/W-0h	R/W-0h	R/W-1h	R/W-1h	R/W-0h	R/W-1h	R/W-1h	R/W-0h

Table 8-96 OSCIMSC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	HFSRCPENDIM	R/W	0h	0: Disable interrupt generation when HFSRCPEND is qualified 1: Enable interrupt generation when HFSRCPEND is qualified
6	LFSRCDONEIM	R/W	0h	0: Disable interrupt generation when LFSRCDONE is qualified 1: Enable interrupt generation when LFSRCDONE is qualified
5	XOSCDLFIM	R/W	1h	0: Disable interrupt generation when XOSCDLF is qualified 1: Enable interrupt generation when XOSCDLF is qualified
4	XOSCLFIM	R/W	1h	0: Disable interrupt generation when XOSCLF is qualified 1: Enable interrupt generation when XOSCLF is qualified
3	RCOSCDLFIM	R/W	0h	0: Disable interrupt generation when RCOSCDLF is qualified 1: Enable interrupt generation when RCOSCDLF is qualified
2	RCOSCLFIM	R/W	1h	0: Disable interrupt generation when RCOSCLF is qualified 1: Enable interrupt generation when RCOSCLF is qualified
1	XOSCHFIM	R/W	1h	0: Disable interrupt generation when XOSCHF is qualified 1: Enable interrupt generation when XOSCHF is qualified
0	RCOSCHFIM	R/W	0h	0: Disable interrupt generation when RCOSCHF is qualified 1: Enable interrupt generation when RCOSCHF is qualified

8.8.2.69 OSCRIS Register (Offset = 294h) [Reset = 00000000h]

OSCRIS is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_OSCRIS_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_OSCRIS_TABLE.

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Oscillator Raw Interrupt Status

Figure 8-92 OSCRIS Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
HFSRCPENDRIS	LFSRCDONERIS	XOSCDLFRIS	XOSCLFRIS	RCOSCDLFRIS	RCOSCLFRIS	XOSCHFRIS	RCOSCHFRIS
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 8-97 OSCRIS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	HFSRCPENDRIS	R	0h	SCLK_HF source switch pending interrupt. After a write to DDI_0_OSC:CTL0.SCLK_HF_SRC_SEL leads to a SCLK_HF source change request, then the requested SCLK_HF source will be enabled and qualified. When the new source is ready to be used as a clock source, then the interrupt HSSRCPENDRIS will go high. When the Flash allows SCLK_HF source switching to take place after flash memory read access is disabled. At this time the actual SCLK_HF clock source switch will be performed, and the interrupt status HSSRCPENDRIS will go low. 0: Indicates SCLK_HF source is not ready to be switched 1: Indicates SCLK_HF source is ready to be switched Interrupt is qualified regardless of OSCIMSC.HFSRCPENDIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.HFSRCPENDC
6	LFSRCDONERIS	R	0h	SCLK_LF source switch done. The DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL register field is used to request that the SCLK_LF source shall be changed. After an SCLK_LF clock source change is requested, the new source may need to be enabled and qualified before switching of clock source can be done. The interrupt LFRSRCDONERIS goes high to indicate that the SCLK_LF clock source switching has been performed. LFRSRCDONERIS will go low again when the next clock source change is requested by writing to DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL . 0: Indicates SCLK_LF source switch has not completed 1: Indicates SCLK_LF source switch has completed Interrupt is qualified regardless of OSCIMSC.LFSRCDONEIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.LFSRCDONEC
5	XOSCDLFRIS	R	0h	The XOSCDLFRIS interrupt indicates when the XOSC_HF oscillator is ready to be used as a derived low-frequency clock source for SCLK_LF or ACLK_REF. When XOSCDLFRIS is high, XOSC_HF will be used as source for SCLK_LF when selected. When none of the system clocks have XOSC_HF selected as clock source, the XOSC_HF source is automatically disabled and the XOSCDLFRIS interrupt status will go low. 0: XOSCDLF has not been qualified 1: XOSCDLF has been qualified Interrupt is qualified regardless of OSCIMSC.XOSCDLFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.XOSCDLFC
4	XOSCLFRIS	R	0h	The XOSCLFRIS interrupt indicates when the output of the XOSC_LF oscillator has been qualified with respect to frequency. The XOSCLFRIS interrupt status goes high when the XOSC_LF oscillator is ready to be used as a clock source. After the clock qualification is successful, XOSCLFRIS interrupt status remains high, and further qualification is turned off until the XOSC_LF oscillator is disabled. XOSCLFRIS interrupt status will go low only at initial power-on, or after the XOSC_LF oscillator has been disabled when being deselected as a clock source. 0: XOSCLF has not been qualified 1: XOSCLF has been qualified Interrupt is qualified regardless of OSCIMSC.XOSCLFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.XOSCLFC
3	RCOSCDLFRIS	R	0h	The RCOSCDLFRIS interrupt indicates when the RCOSC_HF oscillator is ready to be used as a derived low-frequency clock source for SCLK_LF or ACLK_REF. When RCOSCDLFRIS is high, RCOSC_HF will be used as source for SCLK_LF when selected. When none of the system clocks have RCOSC_HF selected as clock source, the RCOSC_HF source is automatically disabled and the RCOSCDLFRIS interrupt status will go low. If the SCLK_LF or ACLK_REF source is changed from RCOSC_HF derived to XOSC_HF derived low-frequency clock and the new source has not been qualified, then the clock will remain running on the original source. The RCOSCDLFRIS interrupt will then remain high. 0: RCOSCDLF has not been qualified 1: RCOSCDLF has been qualified Interrupt is qualified regardless of OSCIMSC.RCOSCDLFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.RCOSCDLFC
2	RCOSCLFRIS	R	0h	The RCOSCLFRIS interrupt indicates when the output of the RCOSC_LF oscillator has been qualified with respect to frequency. The RCOSCLFRIS interrupt status goes high when the RCOSC_LF oscillator is ready to be used as a clock source. After the clock qualification is successful, RCOSCLFRIS interrupt status remains high, and further qualification is turned off until the RCOSC_LF oscillator is disabled. RCOSCLFRIS interrupt status will go low only at initial power-on, or after the RCOSC_LF oscillator has been disabled when being deselected as a clock source. 0: RCOSCLF has not been qualified 1: RCOSCLF has been qualified Interrupt is qualified regardless of OSCIMSC.RCOSCLFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.RCOSCLFC
1	XOSCHFRIS	R	0h	The XOSCHFRIS interrupt indicates when the XOSC_HF oscillator has been qualified for use as a clock source. XOSCHFRIS is also used in TCXO mode (when DDI_0_OSC:XOSCHFCTL.TCXO_MODE is 1). When the XOSCHFRIS interrupt is high, the oscillator is qualified and will be used as a clock source when selected. The XOSCHFRIS interrupt goes low when the oscillator is disabled after being deselected as a clock source. 0: XOSC_HF has not been qualified 1: XOSC_HF has been qualified Interrupt is qualified regardless of OSCIMSC.XOSCHFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.XOSCHFC
0	RCOSCHFRIS	R	0h	The RCOSCHFRIS interrupt indicates when the RCOSC_HF oscillator has been qualified for use as a clock source When the RCOSCHFRIS interrupt is high, the oscillator is qualified and will be used as a clock source when selected. The RCOSCHFRIS interrupt goes low when the oscillator is disabled after being deselected as a clock source. 0: RCOSC_HF has not been qualified 1: RCOSC_HF has been qualified Interrupt is qualified regardless of OSCIMSC.RCOSCHFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.RCOSCHFC

8.8.2.70 OSCICR Register (Offset = 298h) [Reset = 00000000h]

OSCICR is shown in #PRCM_PRCM_REGISTERS_PRCM_ALL_OSCICR_FIGURE and described in #PRCM_PRCM_REGISTERS_PRCM_ALL_OSCICR_TABLE.

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Oscillator Raw Interrupt Clear

Figure 8-93 OSCICR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
HFSRCPENDC	LFSRCDONEC	XOSCDLFC	XOSCLFC	RCOSCDLFC	RCOSCLFC	XOSCHFC	RCOSCHFC
W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h

Table 8-98 OSCICR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	HFSRCPENDC	W	0h	Writing 1 to this field clears the HFSRCPEND raw interrupt status. Writing 0 has no effect.
6	LFSRCDONEC	W	0h	Writing 1 to this field clears the LFSRCDONE raw interrupt status. Writing 0 has no effect.
5	XOSCDLFC	W	0h	Writing 1 to this field clears the XOSCDLF raw interrupt status. Writing 0 has no effect.
4	XOSCLFC	W	0h	Writing 1 to this field clears the XOSCLF raw interrupt status. Writing 0 has no effect.
3	RCOSCDLFC	W	0h	Writing 1 to this field clears the RCOSCDLF raw interrupt status. Writing 0 has no effect.
2	RCOSCLFC	W	0h	Writing 1 to this field clears the RCOSCLF raw interrupt status. Writing 0 has no effect.
1	XOSCHFC	W	0h	Writing 1 to this field clears the XOSCHF raw interrupt status. Writing 0 has no effect.
0	RCOSCHFC	W	0h	Writing 1 to this field clears the RCOSCHF raw interrupt status. Writing 0 has no effect.