SWCU192 User guide | 德州仪器 TI.com.cn

SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

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        382
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                578
        
                579
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    3. 582
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                589
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                602
        
                 603
        
                604
        
                 605
        
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                637
        
                638
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                645
        
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                647
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                649
        
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                668
        
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7. 676
8. 677
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690
1. 691
2. 692
3. 693
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695
1. 696
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3. 698
4. 699
  1. 700
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5. 711
6. 712
7. 713
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715
1. 716
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7. 737
  1. 738
739
1. 740
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    1. 750
  3. 751
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    1. 756
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4. 758
5. 759
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761
1. 762
2. 763
3. 764
4. 765
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  2. 768
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    1. 777
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    1. 779
    2. 780
5. 781
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6. 789
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7. 794
8. 795
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  2. 797
9. 798
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800
1. 801
  1. 802
2. 803
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    1. 807
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  4. 810
    1. 811
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3. 814
  1. 815
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    4. 820
    5. 821
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      1. 826
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    8. 832
  3. 833
    1. 834
      1. 835
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      10. 844
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      12. 846
      13. 847
      14. 848
    2. 849
      1. 850
      2. 851
      3. 852
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      6. 855
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      8. 857
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      12. 861
      13. 862
      14. 863
      15. 864
      16. 865
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      18. 867
      19. 868
      20. 869
  4. 870
    1. 871
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4. 876
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5. 886
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    1. 888
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  2. 892
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    1. 897
      1.        898
        
                899
        
                900
      2. 901
      3. 902
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      5. 904
    2. 905
    3. 906
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    6. 909
  5. 910
    1. 911
    2. 912
    3. 913
    4. 914
    5. 915
    6. 916
6. 917
  1. 918
    1. 919
      1. 920
    2. 921
    3. 922
    4. 923
  2. 924
7. 925
  1. 926
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8. 928
  1. 929
  2. 930
  3. 931
  4. 932
  5. 933
  6. 934
  7. 935
  8. 936
    1. 937
    2. 938
    3. 939
    4. 940
  9. 941
    1. 942
    2. 943
    3. 944
  10. 945
    1. 946
    2. 947
    3. 948
    4. 949
    5. 950
  11. 951
    1. 952
    2. 953
    3. 954
    4. 955
    5. 956
  12. 957
  13. 958
  14. 959
  15. 960
  16. 961
  17. 962
9. 963
  1. 964
10. 965
  1. 966
  2. 967
    1. 968
      1. 969
    2. 970
    3. 971
  3. 972
  4. 973
    1. 974
    2. 975
  5. 976
    1. 977
    2. 978
      1. 979
    3. 980
      1. 981
      2. 982
    4. 983
      1. 984
      2. 985
    5. 986
      1. 987
      2. 988
      3. 989
  6. 990
    1. 991
    2. 992
11. 993
  1. 994
  2. 995
  3. 996
997

14.10.2 MCU_GPIO Registers

#MCU_GPIO_MCU_GPIO_MAP1_TABLE_1 lists the memory-mapped registers for the MCU_GPIO registers. All register offset addresses not listed in #MCU_GPIO_MCU_GPIO_MAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 14-11 MCU_GPIO Registers

Offset	Acronym	Register Name	Section
0h	DOUT3_0	Data Out 0 to 3	#MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT3_0
4h	DOUT7_4	Data Out 4 to 7	#MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT7_4
8h	DOUT11_8	Data Out 8 to 11	#MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT11_8
Ch	DOUT15_12	Data Out 12 to 15	#MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT15_12
10h	DOUT19_16	Data Out 16 to 19	#MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT19_16
14h	DOUT23_20	Data Out 20 to 23	#MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT23_20
18h	DOUT27_24	Data Out 24 to 27	#MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT27_24
1Ch	DOUT31_28	Data Out 28 to 31	#MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT31_28
80h	DOUT31_0	Data Output for DIO 0 to 31	#MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT31_0
90h	DOUTSET31_0	Data Out Set	#MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUTSET31_0
A0h	DOUTCLR31_0	Data Out Clear	#MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUTCLR31_0
B0h	DOUTTGL31_0	Data Out Toggle	#MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUTTGL31_0
C0h	DIN31_0	Data Input from DIO 0 to 31	#MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DIN31_0
D0h	DOE31_0	Data Output Enable for DIO 0 to 31	#MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOE31_0
E0h	EVFLAGS31_0	Event Register for DIO 0 to 31	#MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_EVFLAGS31_0

Complex bit access types are encoded to fit into small table cells. #MCU_GPIO_MCU_GPIO_MAP1_LEGEND shows the codes that are used for access types in this section.

Table 14-12 MCU_GPIO Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
W1C	W 1C	Write 1 to clear
W1S	W 1S	Write 1 to set
Reset or Default Value
-n		Value after reset or the default value

14.10.2.1 DOUT3_0 Register (Offset = 0h) [Reset = 00000000h]

DOUT3_0 is shown in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT3_0_FIGURE and described in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT3_0_TABLE.

Return to the Summary Table.

Data Out 0 to 3
Alias register for byte access to each bit in DOUT31_0

Figure 14-8 DOUT3_0 Register

31	30	29	28	27	26	25	24
RESERVED							DIO3
R-0h							W-0h

23	22	21	20	19	18	17	16
RESERVED							DIO2
R-0h							W-0h

15	14	13	12	11	10	9	8
RESERVED							DIO1
R-0h							W-0h

7	6	5	4	3	2	1	0
RESERVED							DIO0
R-0h							W-0h

Table 14-13 DOUT3_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24	DIO3	W	0h	Sets the state of the pin that is configured as DIO#3, if the corresponding DOE31_0 bitfield is set.
23-17	RESERVED	R	0h	Reserved
16	DIO2	W	0h	Sets the state of the pin that is configured as DIO#2, if the corresponding DOE31_0 bitfield is set.
15-9	RESERVED	R	0h	Reserved
8	DIO1	W	0h	Sets the state of the pin that is configured as DIO#1, if the corresponding DOE31_0 bitfield is set.
7-1	RESERVED	R	0h	Reserved
0	DIO0	W	0h	Sets the state of the pin that is configured as DIO#0, if the corresponding DOE31_0 bitfield is set.

14.10.2.2 DOUT7_4 Register (Offset = 4h) [Reset = 00000000h]

DOUT7_4 is shown in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT7_4_FIGURE and described in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT7_4_TABLE.

Return to the Summary Table.

Data Out 4 to 7
Alias register for byte access to each bit in DOUT31_0

Figure 14-9 DOUT7_4 Register

31	30	29	28	27	26	25	24
RESERVED							DIO7
R-0h							W-0h

23	22	21	20	19	18	17	16
RESERVED							DIO6
R-0h							W-0h

15	14	13	12	11	10	9	8
RESERVED							DIO5
R-0h							W-0h

7	6	5	4	3	2	1	0
RESERVED							DIO4
R-0h							W-0h

Table 14-14 DOUT7_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24	DIO7	W	0h	Sets the state of the pin that is configured as DIO#7, if the corresponding DOE31_0 bitfield is set.
23-17	RESERVED	R	0h	Reserved
16	DIO6	W	0h	Sets the state of the pin that is configured as DIO#6, if the corresponding DOE31_0 bitfield is set.
15-9	RESERVED	R	0h	Reserved
8	DIO5	W	0h	Sets the state of the pin that is configured as DIO#5, if the corresponding DOE31_0 bitfield is set.
7-1	RESERVED	R	0h	Reserved
0	DIO4	W	0h	Sets the state of the pin that is configured as DIO#4, if the corresponding DOE31_0 bitfield is set.

14.10.2.3 DOUT11_8 Register (Offset = 8h) [Reset = 00000000h]

DOUT11_8 is shown in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT11_8_FIGURE and described in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT11_8_TABLE.

Return to the Summary Table.

Data Out 8 to 11
Alias register for byte access to each bit in DOUT31_0

Figure 14-10 DOUT11_8 Register

31	30	29	28	27	26	25	24
RESERVED							DIO11
R-0h							W-0h

23	22	21	20	19	18	17	16
RESERVED							DIO10
R-0h							W-0h

15	14	13	12	11	10	9	8
RESERVED							DIO9
R-0h							W-0h

7	6	5	4	3	2	1	0
RESERVED							DIO8
R-0h							W-0h

Table 14-15 DOUT11_8 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24	DIO11	W	0h	Sets the state of the pin that is configured as DIO#11, if the corresponding DOE31_0 bitfield is set.
23-17	RESERVED	R	0h	Reserved
16	DIO10	W	0h	Sets the state of the pin that is configured as DIO#10, if the corresponding DOE31_0 bitfield is set.
15-9	RESERVED	R	0h	Reserved
8	DIO9	W	0h	Sets the state of the pin that is configured as DIO#9, if the corresponding DOE31_0 bitfield is set.
7-1	RESERVED	R	0h	Reserved
0	DIO8	W	0h	Sets the state of the pin that is configured as DIO#8, if the corresponding DOE31_0 bitfield is set.

14.10.2.4 DOUT15_12 Register (Offset = Ch) [Reset = 00000000h]

DOUT15_12 is shown in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT15_12_FIGURE and described in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT15_12_TABLE.

Return to the Summary Table.

Data Out 12 to 15
Alias register for byte access to each bit in DOUT31_0

Figure 14-11 DOUT15_12 Register

31	30	29	28	27	26	25	24
RESERVED							DIO15
R-0h							W-0h

23	22	21	20	19	18	17	16
RESERVED							DIO14
R-0h							W-0h

15	14	13	12	11	10	9	8
RESERVED							DIO13
R-0h							W-0h

7	6	5	4	3	2	1	0
RESERVED							DIO12
R-0h							W-0h

Table 14-16 DOUT15_12 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24	DIO15	W	0h	Sets the state of the pin that is configured as DIO#15, if the corresponding DOE31_0 bitfield is set.
23-17	RESERVED	R	0h	Reserved
16	DIO14	W	0h	Sets the state of the pin that is configured as DIO#14, if the corresponding DOE31_0 bitfield is set.
15-9	RESERVED	R	0h	Reserved
8	DIO13	W	0h	Sets the state of the pin that is configured as DIO#13, if the corresponding DOE31_0 bitfield is set.
7-1	RESERVED	R	0h	Reserved
0	DIO12	W	0h	Sets the state of the pin that is configured as DIO#12, if the corresponding DOE31_0 bitfield is set.

14.10.2.5 DOUT19_16 Register (Offset = 10h) [Reset = 00000000h]

DOUT19_16 is shown in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT19_16_FIGURE and described in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT19_16_TABLE.

Return to the Summary Table.

Data Out 16 to 19
Alias register for byte access to each bit in DOUT31_0

Figure 14-12 DOUT19_16 Register

31	30	29	28	27	26	25	24
RESERVED							DIO19
R-0h							W-0h

23	22	21	20	19	18	17	16
RESERVED							DIO18
R-0h							W-0h

15	14	13	12	11	10	9	8
RESERVED							DIO17
R-0h							W-0h

7	6	5	4	3	2	1	0
RESERVED							DIO16
R-0h							W-0h

Table 14-17 DOUT19_16 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24	DIO19	W	0h	Sets the state of the pin that is configured as DIO#19, if the corresponding DOE31_0 bitfield is set.
23-17	RESERVED	R	0h	Reserved
16	DIO18	W	0h	Sets the state of the pin that is configured as DIO#18, if the corresponding DOE31_0 bitfield is set.
15-9	RESERVED	R	0h	Reserved
8	DIO17	W	0h	Sets the state of the pin that is configured as DIO#17, if the corresponding DOE31_0 bitfield is set.
7-1	RESERVED	R	0h	Reserved
0	DIO16	W	0h	Sets the state of the pin that is configured as DIO#16, if the corresponding DOE31_0 bitfield is set.

14.10.2.6 DOUT23_20 Register (Offset = 14h) [Reset = 00000000h]

DOUT23_20 is shown in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT23_20_FIGURE and described in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT23_20_TABLE.

Return to the Summary Table.

Data Out 20 to 23
Alias register for byte access to each bit in DOUT31_0

Figure 14-13 DOUT23_20 Register

31	30	29	28	27	26	25	24
RESERVED							DIO23
R-0h							W-0h

23	22	21	20	19	18	17	16
RESERVED							DIO22
R-0h							W-0h

15	14	13	12	11	10	9	8
RESERVED							DIO21
R-0h							W-0h

7	6	5	4	3	2	1	0
RESERVED							DIO20
R-0h							W-0h

Table 14-18 DOUT23_20 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24	DIO23	W	0h	Sets the state of the pin that is configured as DIO#23, if the corresponding DOE31_0 bitfield is set.
23-17	RESERVED	R	0h	Reserved
16	DIO22	W	0h	Sets the state of the pin that is configured as DIO#22, if the corresponding DOE31_0 bitfield is set.
15-9	RESERVED	R	0h	Reserved
8	DIO21	W	0h	Sets the state of the pin that is configured as DIO#21, if the corresponding DOE31_0 bitfield is set.
7-1	RESERVED	R	0h	Reserved
0	DIO20	W	0h	Sets the state of the pin that is configured as DIO#20, if the corresponding DOE31_0 bitfield is set.

14.10.2.7 DOUT27_24 Register (Offset = 18h) [Reset = 00000000h]

DOUT27_24 is shown in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT27_24_FIGURE and described in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT27_24_TABLE.

Return to the Summary Table.

Data Out 24 to 27
Alias register for byte access to each bit in DOUT31_0

Figure 14-14 DOUT27_24 Register

31	30	29	28	27	26	25	24
RESERVED							DIO27
R-0h							W-0h

23	22	21	20	19	18	17	16
RESERVED							DIO26
R-0h							W-0h

15	14	13	12	11	10	9	8
RESERVED							DIO25
R-0h							W-0h

7	6	5	4	3	2	1	0
RESERVED							DIO24
R-0h							W-0h

Table 14-19 DOUT27_24 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24	DIO27	W	0h	Sets the state of the pin that is configured as DIO#27, if the corresponding DOE31_0 bitfield is set.
23-17	RESERVED	R	0h	Reserved
16	DIO26	W	0h	Sets the state of the pin that is configured as DIO#26, if the corresponding DOE31_0 bitfield is set.
15-9	RESERVED	R	0h	Reserved
8	DIO25	W	0h	Sets the state of the pin that is configured as DIO#25, if the corresponding DOE31_0 bitfield is set.
7-1	RESERVED	R	0h	Reserved
0	DIO24	W	0h	Sets the state of the pin that is configured as DIO#24, if the corresponding DOE31_0 bitfield is set.

14.10.2.8 DOUT31_28 Register (Offset = 1Ch) [Reset = 00000000h]

DOUT31_28 is shown in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT31_28_FIGURE and described in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT31_28_TABLE.

Return to the Summary Table.

Data Out 28 to 31
Alias register for byte access to each bit in DOUT31_0

Figure 14-15 DOUT31_28 Register

31	30	29	28	27	26	25	24
RESERVED							DIO31
R-0h							W-0h

23	22	21	20	19	18	17	16
RESERVED							DIO30
R-0h							W-0h

15	14	13	12	11	10	9	8
RESERVED							DIO29
R-0h							W-0h

7	6	5	4	3	2	1	0
RESERVED							DIO28
R-0h							W-0h

Table 14-20 DOUT31_28 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24	DIO31	W	0h	Sets the state of the pin that is configured as DIO#31, if the corresponding DOE31_0 bitfield is set.
23-17	RESERVED	R	0h	Reserved
16	DIO30	W	0h	Sets the state of the pin that is configured as DIO#30, if the corresponding DOE31_0 bitfield is set.
15-9	RESERVED	R	0h	Reserved
8	DIO29	W	0h	Sets the state of the pin that is configured as DIO#29, if the corresponding DOE31_0 bitfield is set.
7-1	RESERVED	R	0h	Reserved
0	DIO28	W	0h	Sets the state of the pin that is configured as DIO#28, if the corresponding DOE31_0 bitfield is set.

14.10.2.9 DOUT31_0 Register (Offset = 80h) [Reset = 00000000h]

DOUT31_0 is shown in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT31_0_FIGURE and described in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUT31_0_TABLE.

Return to the Summary Table.

Data Output for DIO 0 to 31

Figure 14-16 DOUT31_0 Register

31	30	29	28	27	26	25	24
DIO31	DIO30	DIO29	DIO28	DIO27	DIO26	DIO25	DIO24
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
DIO23	DIO22	DIO21	DIO20	DIO19	DIO18	DIO17	DIO16
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
DIO15	DIO14	DIO13	DIO12	DIO11	DIO10	DIO9	DIO8
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
DIO7	DIO6	DIO5	DIO4	DIO3	DIO2	DIO1	DIO0
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 14-21 DOUT31_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	DIO31	R/W	0h	Data output for DIO 31
30	DIO30	R/W	0h	Data output for DIO 30
29	DIO29	R/W	0h	Data output for DIO 29
28	DIO28	R/W	0h	Data output for DIO 28
27	DIO27	R/W	0h	Data output for DIO 27
26	DIO26	R/W	0h	Data output for DIO 26
25	DIO25	R/W	0h	Data output for DIO 25
24	DIO24	R/W	0h	Data output for DIO 24
23	DIO23	R/W	0h	Data output for DIO 23
22	DIO22	R/W	0h	Data output for DIO 22
21	DIO21	R/W	0h	Data output for DIO 21
20	DIO20	R/W	0h	Data output for DIO 20
19	DIO19	R/W	0h	Data output for DIO 19
18	DIO18	R/W	0h	Data output for DIO 18
17	DIO17	R/W	0h	Data output for DIO 17
16	DIO16	R/W	0h	Data output for DIO 16
15	DIO15	R/W	0h	Data output for DIO 15
14	DIO14	R/W	0h	Data output for DIO 14
13	DIO13	R/W	0h	Data output for DIO 13
12	DIO12	R/W	0h	Data output for DIO 12
11	DIO11	R/W	0h	Data output for DIO 11
10	DIO10	R/W	0h	Data output for DIO 10
9	DIO9	R/W	0h	Data output for DIO 9
8	DIO8	R/W	0h	Data output for DIO 8
7	DIO7	R/W	0h	Data output for DIO 7
6	DIO6	R/W	0h	Data output for DIO 6
5	DIO5	R/W	0h	Data output for DIO 5
4	DIO4	R/W	0h	Data output for DIO 4
3	DIO3	R/W	0h	Data output for DIO 3
2	DIO2	R/W	0h	Data output for DIO 2
1	DIO1	R/W	0h	Data output for DIO 1
0	DIO0	R/W	0h	Data output for DIO 0

14.10.2.10 DOUTSET31_0 Register (Offset = 90h) [Reset = 00000000h]

DOUTSET31_0 is shown in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUTSET31_0_FIGURE and described in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUTSET31_0_TABLE.

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Data Out Set
Writing 1 to a bit position sets the corresponding bit in the DOUT31_0 register

Figure 14-17 DOUTSET31_0 Register

31	30	29	28	27	26	25	24
DIO31	DIO30	DIO29	DIO28	DIO27	DIO26	DIO25	DIO24
W1S-0h	W1S-0h	W1S-0h	W1S-0h	W1S-0h	W1S-0h	W1S-0h	W1S-0h

23	22	21	20	19	18	17	16
DIO23	DIO22	DIO21	DIO20	DIO19	DIO18	DIO17	DIO16
W1S-0h	W1S-0h	W1S-0h	W1S-0h	W1S-0h	W1S-0h	W1S-0h	W1S-0h

15	14	13	12	11	10	9	8
DIO15	DIO14	DIO13	DIO12	DIO11	DIO10	DIO9	DIO8
W1S-0h	W1S-0h	W1S-0h	W1S-0h	W1S-0h	W1S-0h	W1S-0h	W1S-0h

7	6	5	4	3	2	1	0
DIO7	DIO6	DIO5	DIO4	DIO3	DIO2	DIO1	DIO0
W1S-0h	W1S-0h	W1S-0h	W1S-0h	W1S-0h	W1S-0h	W1S-0h	W1S-0h

Table 14-22 DOUTSET31_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	DIO31	W1S	0h	Set bit 31
30	DIO30	W1S	0h	Set bit 30
29	DIO29	W1S	0h	Set bit 29
28	DIO28	W1S	0h	Set bit 28
27	DIO27	W1S	0h	Set bit 27
26	DIO26	W1S	0h	Set bit 26
25	DIO25	W1S	0h	Set bit 25
24	DIO24	W1S	0h	Set bit 24
23	DIO23	W1S	0h	Set bit 23
22	DIO22	W1S	0h	Set bit 22
21	DIO21	W1S	0h	Set bit 21
20	DIO20	W1S	0h	Set bit 20
19	DIO19	W1S	0h	Set bit 19
18	DIO18	W1S	0h	Set bit 18
17	DIO17	W1S	0h	Set bit 17
16	DIO16	W1S	0h	Set bit 16
15	DIO15	W1S	0h	Set bit 15
14	DIO14	W1S	0h	Set bit 14
13	DIO13	W1S	0h	Set bit 13
12	DIO12	W1S	0h	Set bit 12
11	DIO11	W1S	0h	Set bit 11
10	DIO10	W1S	0h	Set bit 10
9	DIO9	W1S	0h	Set bit 9
8	DIO8	W1S	0h	Set bit 8
7	DIO7	W1S	0h	Set bit 7
6	DIO6	W1S	0h	Set bit 6
5	DIO5	W1S	0h	Set bit 5
4	DIO4	W1S	0h	Set bit 4
3	DIO3	W1S	0h	Set bit 3
2	DIO2	W1S	0h	Set bit 2
1	DIO1	W1S	0h	Set bit 1
0	DIO0	W1S	0h	Set bit 0

14.10.2.11 DOUTCLR31_0 Register (Offset = A0h) [Reset = 00000000h]

DOUTCLR31_0 is shown in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUTCLR31_0_FIGURE and described in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUTCLR31_0_TABLE.

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Data Out Clear
Writing 1 to a bit position clears the corresponding bit in the DOUT31_0 register

Figure 14-18 DOUTCLR31_0 Register

31	30	29	28	27	26	25	24
DIO31	DIO30	DIO29	DIO28	DIO27	DIO26	DIO25	DIO24
W1C-0h	W1C-0h	W1C-0h	W1C-0h	W1C-0h	W1C-0h	W1C-0h	W1C-0h

23	22	21	20	19	18	17	16
DIO23	DIO22	DIO21	DIO20	DIO19	DIO18	DIO17	DIO16
W1C-0h	W1C-0h	W1C-0h	W1C-0h	W1C-0h	W1C-0h	W1C-0h	W1C-0h

15	14	13	12	11	10	9	8
DIO15	DIO14	DIO13	DIO12	DIO11	DIO10	DIO9	DIO8
W1C-0h	W1C-0h	W1C-0h	W1C-0h	W1C-0h	W1C-0h	W1C-0h	W1C-0h

7	6	5	4	3	2	1	0
DIO7	DIO6	DIO5	DIO4	DIO3	DIO2	DIO1	DIO0
W1C-0h	W1C-0h	W1C-0h	W1C-0h	W1C-0h	W1C-0h	W1C-0h	W1C-0h

Table 14-23 DOUTCLR31_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	DIO31	W1C	0h	Clears bit 31
30	DIO30	W1C	0h	Clears bit 30
29	DIO29	W1C	0h	Clears bit 29
28	DIO28	W1C	0h	Clears bit 28
27	DIO27	W1C	0h	Clears bit 27
26	DIO26	W1C	0h	Clears bit 26
25	DIO25	W1C	0h	Clears bit 25
24	DIO24	W1C	0h	Clears bit 24
23	DIO23	W1C	0h	Clears bit 23
22	DIO22	W1C	0h	Clears bit 22
21	DIO21	W1C	0h	Clears bit 21
20	DIO20	W1C	0h	Clears bit 20
19	DIO19	W1C	0h	Clears bit 19
18	DIO18	W1C	0h	Clears bit 18
17	DIO17	W1C	0h	Clears bit 17
16	DIO16	W1C	0h	Clears bit 16
15	DIO15	W1C	0h	Clears bit 15
14	DIO14	W1C	0h	Clears bit 14
13	DIO13	W1C	0h	Clears bit 13
12	DIO12	W1C	0h	Clears bit 12
11	DIO11	W1C	0h	Clears bit 11
10	DIO10	W1C	0h	Clears bit 10
9	DIO9	W1C	0h	Clears bit 9
8	DIO8	W1C	0h	Clears bit 8
7	DIO7	W1C	0h	Clears bit 7
6	DIO6	W1C	0h	Clears bit 6
5	DIO5	W1C	0h	Clears bit 5
4	DIO4	W1C	0h	Clears bit 4
3	DIO3	W1C	0h	Clears bit 3
2	DIO2	W1C	0h	Clears bit 2
1	DIO1	W1C	0h	Clears bit 1
0	DIO0	W1C	0h	Clears bit 0

14.10.2.12 DOUTTGL31_0 Register (Offset = B0h) [Reset = 00000000h]

DOUTTGL31_0 is shown in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUTTGL31_0_FIGURE and described in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOUTTGL31_0_TABLE.

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Data Out Toggle
Writing 1 to a bit position will invert the corresponding DIO output.

Figure 14-19 DOUTTGL31_0 Register

31	30	29	28	27	26	25	24
DIO31	DIO30	DIO29	DIO28	DIO27	DIO26	DIO25	DIO24
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
DIO23	DIO22	DIO21	DIO20	DIO19	DIO18	DIO17	DIO16
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
DIO15	DIO14	DIO13	DIO12	DIO11	DIO10	DIO9	DIO8
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
DIO7	DIO6	DIO5	DIO4	DIO3	DIO2	DIO1	DIO0
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 14-24 DOUTTGL31_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	DIO31	R/W	0h	Toggles bit 31
30	DIO30	R/W	0h	Toggles bit 30
29	DIO29	R/W	0h	Toggles bit 29
28	DIO28	R/W	0h	Toggles bit 28
27	DIO27	R/W	0h	Toggles bit 27
26	DIO26	R/W	0h	Toggles bit 26
25	DIO25	R/W	0h	Toggles bit 25
24	DIO24	R/W	0h	Toggles bit 24
23	DIO23	R/W	0h	Toggles bit 23
22	DIO22	R/W	0h	Toggles bit 22
21	DIO21	R/W	0h	Toggles bit 21
20	DIO20	R/W	0h	Toggles bit 20
19	DIO19	R/W	0h	Toggles bit 19
18	DIO18	R/W	0h	Toggles bit 18
17	DIO17	R/W	0h	Toggles bit 17
16	DIO16	R/W	0h	Toggles bit 16
15	DIO15	R/W	0h	Toggles bit 15
14	DIO14	R/W	0h	Toggles bit 14
13	DIO13	R/W	0h	Toggles bit 13
12	DIO12	R/W	0h	Toggles bit 12
11	DIO11	R/W	0h	Toggles bit 11
10	DIO10	R/W	0h	Toggles bit 10
9	DIO9	R/W	0h	Toggles bit 9
8	DIO8	R/W	0h	Toggles bit 8
7	DIO7	R/W	0h	Toggles bit 7
6	DIO6	R/W	0h	Toggles bit 6
5	DIO5	R/W	0h	Toggles bit 5
4	DIO4	R/W	0h	Toggles bit 4
3	DIO3	R/W	0h	Toggles bit 3
2	DIO2	R/W	0h	Toggles bit 2
1	DIO1	R/W	0h	Toggles bit 1
0	DIO0	R/W	0h	Toggles bit 0

14.10.2.13 DIN31_0 Register (Offset = C0h) [Reset = 00000000h]

DIN31_0 is shown in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DIN31_0_FIGURE and described in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DIN31_0_TABLE.

Return to the Summary Table.

Data Input from DIO 0 to 31

Figure 14-20 DIN31_0 Register

31	30	29	28	27	26	25	24
DIO31	DIO30	DIO29	DIO28	DIO27	DIO26	DIO25	DIO24
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

23	22	21	20	19	18	17	16
DIO23	DIO22	DIO21	DIO20	DIO19	DIO18	DIO17	DIO16
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

15	14	13	12	11	10	9	8
DIO15	DIO14	DIO13	DIO12	DIO11	DIO10	DIO9	DIO8
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
DIO7	DIO6	DIO5	DIO4	DIO3	DIO2	DIO1	DIO0
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 14-25 DIN31_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	DIO31	R	0h	Data input from DIO 31
30	DIO30	R	0h	Data input from DIO 30
29	DIO29	R	0h	Data input from DIO 29
28	DIO28	R	0h	Data input from DIO 28
27	DIO27	R	0h	Data input from DIO 27
26	DIO26	R	0h	Data input from DIO 26
25	DIO25	R	0h	Data input from DIO 25
24	DIO24	R	0h	Data input from DIO 24
23	DIO23	R	0h	Data input from DIO 23
22	DIO22	R	0h	Data input from DIO 22
21	DIO21	R	0h	Data input from DIO 21
20	DIO20	R	0h	Data input from DIO 20
19	DIO19	R	0h	Data input from DIO 19
18	DIO18	R	0h	Data input from DIO 18
17	DIO17	R	0h	Data input from DIO 17
16	DIO16	R	0h	Data input from DIO 16
15	DIO15	R	0h	Data input from DIO 15
14	DIO14	R	0h	Data input from DIO 14
13	DIO13	R	0h	Data input from DIO 13
12	DIO12	R	0h	Data input from DIO 12
11	DIO11	R	0h	Data input from DIO 11
10	DIO10	R	0h	Data input from DIO 10
9	DIO9	R	0h	Data input from DIO 9
8	DIO8	R	0h	Data input from DIO 8
7	DIO7	R	0h	Data input from DIO 7
6	DIO6	R	0h	Data input from DIO 6
5	DIO5	R	0h	Data input from DIO 5
4	DIO4	R	0h	Data input from DIO 4
3	DIO3	R	0h	Data input from DIO 3
2	DIO2	R	0h	Data input from DIO 2
1	DIO1	R	0h	Data input from DIO 1
0	DIO0	R	0h	Data input from DIO 0

14.10.2.14 DOE31_0 Register (Offset = D0h) [Reset = 00000000h]

DOE31_0 is shown in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOE31_0_FIGURE and described in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_DOE31_0_TABLE.

Return to the Summary Table.

Data Output Enable for DIO 0 to 31

Figure 14-21 DOE31_0 Register

31	30	29	28	27	26	25	24
DIO31	DIO30	DIO29	DIO28	DIO27	DIO26	DIO25	DIO24
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
DIO23	DIO22	DIO21	DIO20	DIO19	DIO18	DIO17	DIO16
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
DIO15	DIO14	DIO13	DIO12	DIO11	DIO10	DIO9	DIO8
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
DIO7	DIO6	DIO5	DIO4	DIO3	DIO2	DIO1	DIO0
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 14-26 DOE31_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	DIO31	R/W	0h	Data output enable for DIO 31
30	DIO30	R/W	0h	Data output enable for DIO 30
29	DIO29	R/W	0h	Data output enable for DIO 29
28	DIO28	R/W	0h	Data output enable for DIO 28
27	DIO27	R/W	0h	Data output enable for DIO 27
26	DIO26	R/W	0h	Data output enable for DIO 26
25	DIO25	R/W	0h	Data output enable for DIO 25
24	DIO24	R/W	0h	Data output enable for DIO 24
23	DIO23	R/W	0h	Data output enable for DIO 23
22	DIO22	R/W	0h	Data output enable for DIO 22
21	DIO21	R/W	0h	Data output enable for DIO 21
20	DIO20	R/W	0h	Data output enable for DIO 20
19	DIO19	R/W	0h	Data output enable for DIO 19
18	DIO18	R/W	0h	Data output enable for DIO 18
17	DIO17	R/W	0h	Data output enable for DIO 17
16	DIO16	R/W	0h	Data output enable for DIO 16
15	DIO15	R/W	0h	Data output enable for DIO 15
14	DIO14	R/W	0h	Data output enable for DIO 14
13	DIO13	R/W	0h	Data output enable for DIO 13
12	DIO12	R/W	0h	Data output enable for DIO 12
11	DIO11	R/W	0h	Data output enable for DIO 11
10	DIO10	R/W	0h	Data output enable for DIO 10
9	DIO9	R/W	0h	Data output enable for DIO 9
8	DIO8	R/W	0h	Data output enable for DIO 8
7	DIO7	R/W	0h	Data output enable for DIO 7
6	DIO6	R/W	0h	Data output enable for DIO 6
5	DIO5	R/W	0h	Data output enable for DIO 5
4	DIO4	R/W	0h	Data output enable for DIO 4
3	DIO3	R/W	0h	Data output enable for DIO 3
2	DIO2	R/W	0h	Data output enable for DIO 2
1	DIO1	R/W	0h	Data output enable for DIO 1
0	DIO0	R/W	0h	Data output enable for DIO 0

14.10.2.15 EVFLAGS31_0 Register (Offset = E0h) [Reset = 00000000h]

EVFLAGS31_0 is shown in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_EVFLAGS31_0_FIGURE and described in #MCU_GPIO_MCU_GPIO_MAP1_MCU_GPIO_ALL_EVFLAGS31_0_TABLE.

Return to the Summary Table.

Event Register for DIO 0 to 31
Reading this registers will return 1 for triggered event and 0 for non-triggered events.
Writing a 1 to a bit field will clear the event.
The configuration of events is done inside MCU IOC, e.g. events for DIO #0 is configured in IOC:IOCFG0.EDGE_DET and IOC:IOCFG0.EDGE_IRQ_EN.

Figure 14-22 EVFLAGS31_0 Register

31	30	29	28	27	26	25	24
DIO31	DIO30	DIO29	DIO28	DIO27	DIO26	DIO25	DIO24
R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h

23	22	21	20	19	18	17	16
DIO23	DIO22	DIO21	DIO20	DIO19	DIO18	DIO17	DIO16
R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h

15	14	13	12	11	10	9	8
DIO15	DIO14	DIO13	DIO12	DIO11	DIO10	DIO9	DIO8
R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h

7	6	5	4	3	2	1	0
DIO7	DIO6	DIO5	DIO4	DIO3	DIO2	DIO1	DIO0
R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h

Table 14-27 EVFLAGS31_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	DIO31	R/W1C	0h	Event for DIO 31
30	DIO30	R/W1C	0h	Event for DIO 30
29	DIO29	R/W1C	0h	Event for DIO 29
28	DIO28	R/W1C	0h	Event for DIO 28
27	DIO27	R/W1C	0h	Event for DIO 27
26	DIO26	R/W1C	0h	Event for DIO 26
25	DIO25	R/W1C	0h	Event for DIO 25
24	DIO24	R/W1C	0h	Event for DIO 24
23	DIO23	R/W1C	0h	Event for DIO 23
22	DIO22	R/W1C	0h	Event for DIO 22
21	DIO21	R/W1C	0h	Event for DIO 21
20	DIO20	R/W1C	0h	Event for DIO 20
19	DIO19	R/W1C	0h	Event for DIO 19
18	DIO18	R/W1C	0h	Event for DIO 18
17	DIO17	R/W1C	0h	Event for DIO 17
16	DIO16	R/W1C	0h	Event for DIO 16
15	DIO15	R/W1C	0h	Event for DIO 15
14	DIO14	R/W1C	0h	Event for DIO 14
13	DIO13	R/W1C	0h	Event for DIO 13
12	DIO12	R/W1C	0h	Event for DIO 12
11	DIO11	R/W1C	0h	Event for DIO 11
10	DIO10	R/W1C	0h	Event for DIO 10
9	DIO9	R/W1C	0h	Event for DIO 9
8	DIO8	R/W1C	0h	Event for DIO 8
7	DIO7	R/W1C	0h	Event for DIO 7
6	DIO6	R/W1C	0h	Event for DIO 6
5	DIO5	R/W1C	0h	Event for DIO 5
4	DIO4	R/W1C	0h	Event for DIO 4
3	DIO3	R/W1C	0h	Event for DIO 3
2	DIO2	R/W1C	0h	Event for DIO 2
1	DIO1	R/W1C	0h	Event for DIO 1
0	DIO0	R/W1C	0h	Event for DIO 0