SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
| Address Offset | Reset | 0x0000 0000 | |
| Physical Address | Instance | ||
| Description | |||
| The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode. This register is accessible only in privileged mode. | |||
| Handler mode always uses MSP, so the processor ignores
explicit writes to the ASP bit of the CONTROL register when in
handler mode. The exception entry and return mechanisms
automatically update the CONTROL register based on the EXC_RETURN
value (see Table 6-2). In an OS environment, threads running in thread mode must use the process stack and the kernel and exception handlers must use the main stack. By default, thread mode uses MSP. To switch the stack pointer used in thread mode to PSP, either use the MSR instruction to set the ASP bit, as detailed in the Cortex-M3/M4F Instruction Set Technical User's Manual, or perform an exception return to thread mode with the appropriate EXC_RETURN value, as shown in Table 6-2. |
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| When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction, ensuring that instructions after the ISB instruction executes use the new stack pointer. See the Cortex-M3/M4F Instruction Set Technical User's Manual. | |||
| Type | R/W | ||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ASP | TMPL | |||||||||||||||||||||||||||||
| Bits | Field Name | Description | Type | Reset | |
|---|---|---|---|---|---|
| 31–2 | RESERVED | Reserved | R/O | 0x0000 000 | |
| 1 | ASP | Active Stack Pointer | R/W | 0 | |
| Value | Description | ||||
| 1 | PSP is the current stack pointer. | ||||
| 0 | MSP is the current stack pointer. | ||||
| In handler mode, this bit reads as zero and ignores writes. The Arm Cortex-M4F updates this bit automatically on exception return. | |||||
| 0 | TMPL | Thread Mode Privilege Level | R/W | 0 | |
| Value | Description | ||||
| 1 | Unprivileged software can be executed in thread mode. | ||||
| 0 | Only privileged software can be executed in thread mode. | ||||