The exception types are:
- Reset: Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops (potentially at any point in an instruction). When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in thread mode.
- Hard Fault: A hard fault is an exception that occurs because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. Hard faults have a fixed priority of –1, meaning they have higher priority than any exception with configurable priority.
- Bus Fault: A bus fault is an exception that occurs because of a memory-related fault for an instruction or data memory transaction such as a prefetch fault or a memory access fault. This fault can be enabled or disabled.
- Usage Fault: A usage fault is an exception that occurs because of a fault related to instruction execution, such as the following:
- An undefined instruction
- An illegal unaligned access
- Invalid state on instruction execution
- An error on exception return
An unaligned address on a word or halfword memory access or division by 0 can cause a usage fault when the core is properly configured. - SVCall: A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers.
- Debug Monitor: This exception is caused by the debug monitor (when not halting). This exception is active only when enabled. This exception does not activate if it is a lower priority than the current activation.
- PendSV: PendSV is a pendable, interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active. PendSV is triggered using the Interrupt Control and State CPU_SCS:ICSR register.
- SysTick: A SysTick exception is generated by the system timer when it reaches 0 and is enabled to generate an interrupt. Software can also generate a SysTick exception using the Interrupt Control and State register, CPU_SCS:ICSR. In an OS environment, the processor can use this exception as system tick.
- Interrupt (IRQ): An interrupt, or IRQ, is
an exception signaled by a peripheral or generated by a software request and fed
through the NVIC (prioritized). All interrupts are asynchronous to instruction
execution. In the system, peripherals use interrupts to communicate with the
processor. Table 6-7 lists the interrupts on the controller of the C CC13x2x7 and
CC26x2x7
device platform.
For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions
that Table 6-1 shows as having configurable priority (see the CPU_SCS:SHCSR register and the
CPU_SCS:NVIC_ICER0 register in Section 3.9.4).
See Section 6.2 for more information about hard faults, bus faults, and usage faults.
Table 6-1 Exception Types| Exception Type | Vector Number | Priority(1) | Vector Address or
Offset(2) | Activation |
|---|
| — | 0 | — | 0x0000 0000 | Stack top is loaded from the first entry of the vector table on reset. |
| Reset | 1 | –3 (highest) | 0x0000 0004 | Asynchronous |
| — | — | — | — | — |
| Hard fault | 3 | –1 | 0x0000 000C | — |
| Bus fault | 5 | Programmable(3) | 0x0000 0014 | Synchronous when precise and asynchronous when imprecise |
| Usage fault | 6 | Programmable | 0x0000 0018 | Synchronous |
| — | 7 to 10 | — | — | Reserved |
| SVCall | 11 | Programmable | 0x0000 002C | Synchronous |
| Debug monitor | 12 | Programmable | 0x0000 0030 | Synchronous |
| — | 13 | — | — | Reserved |
| PendSV | 14 | Programmable | 0x0000 0038 | Asynchronous |
| SysTick | 15 | Programmable | 0x0000 003C | Asynchronous |
| Interrupts | 16 and above | Programmable(4) | 0x0000 0040 and above | Asynchronous |
(1) 0 is the default priority for all the programmable priorities.