SWCU192 User guide | 德州仪器 TI.com.cn

SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

1
1. 2
2. 3
3. 4
4. 5
5. 6
7
1. 8
2. 9
3. 10
  1. 11
    1. 12
    2. 13
    3. 14
    4. 15
  2. 16
    1. 17
    2. 18
    3. 19
  3. 20
  4. 21
  5. 22
    1. 23
    2. 24
  6. 25
  7. 26
  8. 27
    1. 28
    2. 29
    3. 30
    4. 31
  9. 32
  10. 33
  11. 34
  12. 35
  13. 36
    1. 37
      1. 38
      2. 39
      3. 40
      4. 41
    2. 42
43
1. 44
2. 45
3. 46
  1. 47
  2. 48
  3. 49
  4. 50
  5. 51
  6. 52
4. 53
  1. 54
  2. 55
  3. 56
  4. 57
5. 58
  1. 59
  2. 60
    1. 61
    2. 62
    3. 63
    4. 64
    5. 65
    6. 66
    7. 67
    8. 68
    9. 69
    10. 70
    11. 71
    12. 72
    13. 73
    14. 74
    15. 75
    16. 76
    17. 77
    18. 78
    19. 79
    20. 80
    21. 81
6. 82
  1. 83
  2. 84
  3. 85
7. 86
  1. 87
  2. 88
    1. 89
    2. 90
      1. 91
      2. 92
      3. 93
    3. 94
    4. 95
    5. 96
    6. 97
      1. 98
      2. 99
      3. 100
    7. 101
  3. 102
    1. 103
      1. 104
8. 105
  1. 106
  2. 107
  3. 108
9. 109
  1. 110
  2. 111
  3. 112
  4. 113
  5. 114
115
1. 116
117
1. 118
2. 119
  1. 120
  2. 121
    1. 122
    2. 123
  3. 124
  4. 125
  5. 126
  6. 127
  7. 128
129
1. 130
  1. 131
  2. 132
  3. 133
  4. 134
  5. 135
  6. 136
  7. 137
    1. 138
    2. 139
2. 140
  1. 141
  2. 142
  3. 143
  4. 144
3. 145
  1. 146
  2. 147
    1. 148
4. 149
  1. 150
  2. 151
    1. 152
    2. 153
    3. 154
5. 155
  1. 156
  2. 157
    1. 158
    2. 159
    3. 160
6. 161
7. 162
  1. 163
  2. 164
165
1. 166
2. 167
  1. 168
    1. 169
  2. 170
    1. 171
    2. 172
    3. 173
3. 174
  1. 175
    1. 176
    2. 177
  2. 178
    1. 179
    2. 180
    3. 181
    4. 182
    5. 183
    6. 184
    7. 185
    8. 186
  3. 187
  4. 188
    1. 189
      1. 190
      2. 191
      3. 192
    2. 193
      1. 194
    3. 195
      1. 196
4. 197
5. 198
6. 199
7. 200
8. 201
9. 202
10. 203
204
1. 205
2. 206
3. 207
  1. 208
4. 209
  1. 210
    1. 211
  2. 212
    1. 213
5. 214
  1. 215
    1. 216
  2. 217
    1. 218
    2. 219
    3. 220
  3. 221
6. 222
  1. 223
  2. 224
  3. 225
  4. 226
  5. 227
7. 228
  1. 229
    1. 230
    2. 231
    3. 232
  2. 233
  3. 234
8. 235
  1. 236
  2. 237
  3. 238
239
1. 240
2. 241
  1. 242
    1. 243
    2. 244
    3. 245
  2. 246
  3. 247
  4. 248
3. 249
  1. 250
  2. 251
    1. 252
    2. 253
    3. 254
4. 255
5. 256
  1. 257
  2. 258
  3. 259
  4. 260
6. 261
7. 262
  1. 263
  2. 264
265
1. 266
2. 267
3. 268
4. 269
5. 270
6. 271
7. 272
  1. 273
  2. 274
275
1. 276
  1. 277
  2. 278
2. 279
  1. 280
    1. 281
  2. 282
    1. 283
      1. 284
    2. 285
  3. 286
    1. 287
    2. 288
    3. 289
    4. 290
    5. 291
    6. 292
    7. 293
    8. 294
    9. 295
    10. 296
    11. 297
    12. 298
    13. 299
300
1. 301
2. 302
  1. 303
3. 304
4. 305
  1. 306
307
1. 308
2. 309
  1. 310
  2. 311
3. 312
4. 313
  1. 314
  2. 315
  3. 316
5. 317
  1. 318
  2. 319
  3. 320
    1. 321
    2. 322
  4. 323
    1. 324
      1. 325
    2. 326
      1. 327
    3. 328
  5. 329
    1. 330
    2. 331
    3. 332
    4. 333
    5. 334
  6. 335
    1. 336
    2. 337
    3. 338
    4. 339
    5. 340
6. 341
  1. 342
  2. 343
7. 344
  1. 345
  2. 346
    1. 347
    2. 348
    3. 349
  3. 350
    1. 351
    2. 352
      1. 353
      2. 354
      3. 355
    3. 356
      1. 357
    4. 358
      1. 359
      2. 360
  4. 361
    1. 362
    2. 363
      1. 364
    3. 365
      1. 366
      2. 367
      3. 368
      4. 369
    4. 370
      1. 371
    5. 372
      1. 373
    6. 374
      1. 375
  5. 376
    1. 377
    2. 378
    3. 379
      1. 380
      2. 381
        
        382
      3.        383
        
                384
        
                385
        
                 386
        
                 387
        
                 388
        
                 389
        
                 390
        
                 391
        
                 392
        
                 393
        
                394
        
                395
        
                396
8. 397
  1. 398
    1. 399
    2. 400
  2. 401
9. 402
  1. 403
404
1. 405
2. 406
3. 407
  1. 408
  2. 409
  3. 410
  4. 411
4. 412
  1. 413
5. 414
6. 415
7. 416
8. 417
9. 418
  1. 419
    1. 420
    2. 421
10. 422
  1. 423
  2. 424
  3. 425
426
1. 427
2. 428
3. 429
  1. 430
  2. 431
  3. 432
  4. 433
    1. 434
    2. 435
  5. 436
  6. 437
    1. 438
    2. 439
    3. 440
    4. 441
    5. 442
    6. 443
  7. 444
  8. 445
  9. 446
  10. 447
4. 448
  1. 449
  2. 450
    1. 451
    2. 452
    3. 453
5. 454
  1. 455
456
1. 457
2. 458
3. 459
  1. 460
  2. 461
    1. 462
    2. 463
    3. 464
    4. 465
    5. 466
  3. 467
  4. 468
4. 469
  1. 470
  2. 471
  3. 472
  4. 473
  5. 474
5. 475
  1. 476
477
1. 478
2. 479
  1. 480
  2. 481
  3. 482
    1. 483
  4. 484
3. 485
  1. 486
  2. 487
  3. 488
4. 489
  1. 490
491
1. 492
2. 493
3. 494
4. 495
  1. 496
497
1. 498
2. 499
3. 500
4. 501
5. 502
  1. 503
  2. 504
  3. 505
6. 506
  1. 507
    1. 508
    2. 509
    3. 510
      1. 511
      2. 512
7. 513
  1. 514
515
1. 516
  1. 517
2. 518
  1. 519
    1. 520
  2. 521
    1. 522
    2. 523
  3. 524
  4. 525
3. 526
  1. 527
    1. 528
    2. 529
    3. 530
    4. 531
  2. 532
    1. 533
      1. 534
    2. 535
      1. 536
      2. 537
    3. 538
      1. 539
    4. 540
      1. 541
      2. 542
      3. 543
    5. 544
    6. 545
    7. 546
    8. 547
    9. 548
    10. 549
4. 550
  1. 551
    1. 552
  2. 553
    1. 554
    2. 555
      1. 556
      2. 557
      3. 558
      4. 559
      5. 560
  3. 561
    1. 562
    2. 563
    3. 564
  4. 565
    1. 566
    2. 567
      1. 568
      2. 569
      3. 570
  5. 571
    1. 572
    2. 573
      1. 574
      2. 575
      3. 576
      4.        577
        
                578
        
                579
      5. 580
      6. 581
    3. 582
      1. 583
      2. 584
      3.        585
        
                586
        
                587
        
                588
        
                589
      4. 590
  6. 591
    1. 592
    2. 593
  7. 594
    1. 595
    2. 596
      1. 597
      2. 598
      3. 599
      4. 600
      5.        601
        
                602
        
                 603
        
                604
        
                 605
        
                606
        
                 607
      6. 608
5. 609
  1. 610
    1. 611
    2. 612
  2. 613
    1. 614
    2. 615
      1. 616
      2. 617
      3. 618
      4. 619
      5. 620
      6. 621
      7. 622
      8. 623
  3. 624
    1. 625
    2. 626
      1. 627
      2. 628
      3. 629
      4. 630
  4. 631
    1. 632
    2. 633
      1. 634
      2. 635
      3.        636
        
                637
        
                638
  5. 639
    1. 640
    2. 641
      1. 642
      2. 643
      3.        644
        
                645
        
                646
        
                647
      4.        648
        
                649
        
                650
        
                651
        
                652
      5. 653
      6. 654
  6. 655
    1. 656
    2. 657
      1. 658
      2. 659
      3. 660
      4. 661
      5. 662
6. 663
  1. 664
    1. 665
    2. 666
      1.        667
        
                668
        
                669
  2. 670
  3. 671
  4. 672
  5. 673
  6. 674
  7. 675
7. 676
8. 677
  1. 678
  2. 679
  3. 680
  4. 681
  5. 682
  6. 683
  7. 684
  8. 685
  9. 686
  10. 687
  11. 688
  12. 689
690
1. 691
2. 692
3. 693
  1. 694
695
1. 696
2. 697
3. 698
4. 699
  1. 700
  2. 701
  3. 702
  4. 703
    1. 704
    2. 705
      1. 706
      2. 707
  5. 708
  6. 709
  7. 710
5. 711
6. 712
7. 713
  1. 714
715
1. 716
2. 717
3. 718
4. 719
  1. 720
  2. 721
    1. 722
    2. 723
  3. 724
  4. 725
    1. 726
    2. 727
      1. 728
      2. 729
    3. 730
    4. 731
    5. 732
    6. 733
    7. 734
5. 735
6. 736
7. 737
  1. 738
739
1. 740
2. 741
3. 742
  1. 743
    1. 744
    2. 745
    3. 746
    4. 747
    5. 748
  2. 749
    1. 750
  3. 751
    1. 752
    2. 753
  4. 754
  5. 755
    1. 756
    2. 757
4. 758
5. 759
  1. 760
761
1. 762
2. 763
3. 764
4. 765
  1. 766
    1. 767
  2. 768
  3. 769
  4. 770
    1. 771
  5. 772
    1. 773
  6. 774
    1. 775
  7. 776
    1. 777
  8. 778
    1. 779
    2. 780
5. 781
  1. 782
  2. 783
  3. 784
  4. 785
    1. 786
    2. 787
    3. 788
6. 789
  1. 790
  2. 791
  3. 792
  4. 793
7. 794
8. 795
  1. 796
  2. 797
9. 798
  1. 799
800
1. 801
  1. 802
2. 803
  1. 804
  2. 805
  3. 806
    1. 807
    2. 808
    3. 809
  4. 810
    1. 811
    2. 812
    3. 813
3. 814
  1. 815
  2. 816
    1. 817
    2. 818
    3. 819
    4. 820
    5. 821
      1. 822
      2. 823
      3. 824
    6. 825
      1. 826
    7. 827
      1. 828
      2. 829
      3. 830
      4. 831
    8. 832
  3. 833
    1. 834
      1. 835
      2. 836
      3. 837
      4. 838
      5. 839
      6. 840
      7. 841
      8. 842
      9. 843
      10. 844
      11. 845
      12. 846
      13. 847
      14. 848
    2. 849
      1. 850
      2. 851
      3. 852
      4. 853
      5. 854
      6. 855
      7. 856
      8. 857
      9. 858
      10. 859
      11. 860
      12. 861
      13. 862
      14. 863
      15. 864
      16. 865
      17. 866
      18. 867
      19. 868
      20. 869
  4. 870
    1. 871
    2. 872
    3. 873
    4. 874
    5. 875
4. 876
  1. 877
    1. 878
    2. 879
    3. 880
    4. 881
    5. 882
  2. 883
    1. 884
    2. 885
5. 886
  1. 887
    1. 888
    2. 889
    3. 890
    4. 891
  2. 892
  3. 893
    1. 894
    2. 895
  4. 896
    1. 897
      1.        898
        
                899
        
                900
      2. 901
      3. 902
      4. 903
      5. 904
    2. 905
    3. 906
    4. 907
    5. 908
    6. 909
  5. 910
    1. 911
    2. 912
    3. 913
    4. 914
    5. 915
    6. 916
6. 917
  1. 918
    1. 919
      1. 920
    2. 921
    3. 922
    4. 923
  2. 924
7. 925
  1. 926
  2. 927
8. 928
  1. 929
  2. 930
  3. 931
  4. 932
  5. 933
  6. 934
  7. 935
  8. 936
    1. 937
    2. 938
    3. 939
    4. 940
  9. 941
    1. 942
    2. 943
    3. 944
  10. 945
    1. 946
    2. 947
    3. 948
    4. 949
    5. 950
  11. 951
    1. 952
    2. 953
    3. 954
    4. 955
    5. 956
  12. 957
  13. 958
  14. 959
  15. 960
  16. 961
  17. 962
9. 963
  1. 964
10. 965
  1. 966
  2. 967
    1. 968
      1. 969
    2. 970
    3. 971
  3. 972
  4. 973
    1. 974
    2. 975
  5. 976
    1. 977
    2. 978
      1. 979
    3. 980
      1. 981
      2. 982
    4. 983
      1. 984
      2. 985
    5. 986
      1. 987
      2. 988
      3. 989
  6. 990
    1. 991
    2. 992
11. 993
  1. 994
  2. 995
  3. 996
997

20.8.6 AUX_TIMER01 Registers

#AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_TABLE_1 lists the memory-mapped registers for the AUX_TIMER01 registers. All register offset addresses not listed in #AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 20-125 AUX_TIMER01 Registers

Offset	Acronym	Register Name	Section
0h	T0CFG	Timer 0 Configuration	#AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T0CFG
4h	T0CTL	Timer 0 Control	#AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T0CTL
8h	T0TARGET	Timer 0 Target	#AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T0TARGET
Ch	T0CNTR	Timer 0 Counter	#AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T0CNTR
10h	T1CFG	Timer 1 Configuration	#AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T1CFG
14h	T1CTL	Timer 1 Control	#AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T1CTL
18h	T1TARGET	Timer 1 Target	#AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T1TARGET
1Ch	T1CNTR	Timer 1 Counter	#AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T1CNTR

Complex bit access types are encoded to fit into small table cells. #AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_LEGEND shows the codes that are used for access types in this section.

Table 20-126 AUX_TIMER01 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

20.8.6.1 T0CFG Register (Offset = 0h) [Reset = 00000000h]

T0CFG is shown in #AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T0CFG_FIGURE and described in #AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T0CFG_TABLE.

Return to the Summary Table.

Timer 0 Configuration

Figure 20-111 T0CFG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED	TICK_SRC_POL	TICK_SRC
R-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
PRE				RESERVED		MODE	RELOAD
R/W-0h				R-0h		R/W-0h	R/W-0h

Table 20-127 T0CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-15	RESERVED	R	0h	Reserved
14	TICK_SRC_POL	R/W	0h	Tick source polarity for Timer 0. 0h = Count on rising edges of TICK_SRC. 1h = Count on falling edges of TICK_SRC.
13-8	TICK_SRC	R/W	0h	Select Timer 0 tick source from the synchronous event bus. 0h = AUX_EVCTL:EVSTAT0.AUXIO0 1h = AUX_EVCTL:EVSTAT0.AUXIO1 2h = AUX_EVCTL:EVSTAT0.AUXIO2 3h = AUX_EVCTL:EVSTAT0.AUXIO3 4h = AUX_EVCTL:EVSTAT0.AUXIO4 5h = AUX_EVCTL:EVSTAT0.AUXIO5 6h = AUX_EVCTL:EVSTAT0.AUXIO6 7h = AUX_EVCTL:EVSTAT0.AUXIO7 8h = AUX_EVCTL:EVSTAT0.AUXIO8 9h = AUX_EVCTL:EVSTAT0.AUXIO9 Ah = AUX_EVCTL:EVSTAT0.AUXIO10 Bh = AUX_EVCTL:EVSTAT0.AUXIO11 Ch = AUX_EVCTL:EVSTAT0.AUXIO12 Dh = AUX_EVCTL:EVSTAT0.AUXIO13 Eh = AUX_EVCTL:EVSTAT0.AUXIO14 Fh = AUX_EVCTL:EVSTAT0.AUXIO15 10h = AUX_EVCTL:EVSTAT1.AUXIO16 11h = AUX_EVCTL:EVSTAT1.AUXIO17 12h = AUX_EVCTL:EVSTAT1.AUXIO18 13h = AUX_EVCTL:EVSTAT1.AUXIO19 14h = AUX_EVCTL:EVSTAT1.AUXIO20 15h = AUX_EVCTL:EVSTAT1.AUXIO21 16h = AUX_EVCTL:EVSTAT1.AUXIO22 17h = AUX_EVCTL:EVSTAT1.AUXIO23 18h = AUX_EVCTL:EVSTAT1.AUXIO24 19h = AUX_EVCTL:EVSTAT1.AUXIO25 1Ah = AUX_EVCTL:EVSTAT1.AUXIO26 1Bh = AUX_EVCTL:EVSTAT1.AUXIO27 1Ch = AUX_EVCTL:EVSTAT1.AUXIO28 1Dh = AUX_EVCTL:EVSTAT1.AUXIO29 1Eh = AUX_EVCTL:EVSTAT1.AUXIO30 1Fh = AUX_EVCTL:EVSTAT1.AUXIO31 20h = AUX_EVCTL:EVSTAT2.MANUAL_EV 21h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2 22h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY 23h = AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ 24h = AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD 25h = AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD 26h = AUX_EVCTL:EVSTAT2.SCLK_LF 27h = AUX_EVCTL:EVSTAT2.PWR_DWN 28h = AUX_EVCTL:EVSTAT2.MCU_ACTIVE 29h = AUX_EVCTL:EVSTAT2.VDDR_RECHARGE 2Ah = AUX_EVCTL:EVSTAT2.ACLK_REF 2Bh = AUX_EVCTL:EVSTAT2.MCU_EV 2Ch = AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 2Dh = AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 2Eh = AUX_EVCTL:EVSTAT2.AUX_COMPA 2Fh = AUX_EVCTL:EVSTAT2.AUX_COMPB 30h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 31h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 32h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 33h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 34h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE 35h = AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV 36h = No event. 37h = AUX_EVCTL:EVSTAT3.AUX_TDC_DONE 38h = AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N 39h = AUX_EVCTL:EVSTAT3.AUX_ADC_DONE 3Ah = AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ 3Bh = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL 3Ch = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY 3Dh = AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE 3Eh = AUX_EVCTL:EVSTAT3.AUX_DAC_HOLD_ACTIVE 3Fh = AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY
7-4	PRE	R/W	0h	Prescaler division ratio is 2^PRE: 0x0: Divide by 1. 0x1: Divide by 2. 0x2: Divide by 4. ... 0xF: Divide by 32,768.
3-2	RESERVED	R	0h	Reserved
1	MODE	R/W	0h	Timer 0 mode. Configure source for Timer 0 prescaler. 0h = Use clock as source for prescaler. Note that AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the clock frequency. 1h = Use event set by TICK_SRC as source for prescaler.
0	RELOAD	R/W	0h	Timer 0 reload mode. 0h = Manual mode. Timer 0 stops and T0CTL.EN becomes 0 when the counter value becomes equal to or greater than T0TARGET.VALUE. 1h = Continuous mode. Timer 0 restarts when the counter value becomes equal to or greater than ( T0TARGET.VALUE - 1).

20.8.6.2 T0CTL Register (Offset = 4h) [Reset = 00000000h]

T0CTL is shown in #AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T0CTL_FIGURE and described in #AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T0CTL_TABLE.

Return to the Summary Table.

Timer 0 Control

Figure 20-112 T0CTL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															EN
R-0h															R/W-0h

Table 20-128 T0CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	EN	R/W	0h	Timer 0 enable. 0: Disable Timer 0. 1: Enable Timer 0. The counter restarts from 0 when you enable Timer 0.

20.8.6.3 T0TARGET Register (Offset = 8h) [Reset = 00000000h]

T0TARGET is shown in #AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T0TARGET_FIGURE and described in #AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T0TARGET_TABLE.

Return to the Summary Table.

Timer 0 Target

Figure 20-113 T0TARGET Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																VALUE
R-0h																R/W-0h

Table 20-129 T0TARGET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	VALUE	R/W	0h	Timer 0 target value. Manual Reload Mode: - Timer 0 increments until the counter value becomes equal to or greater than VALUE. - AUX_TIMER0_EV pulses high for 1 peripheral clock period when the counter value is equal to or greater than VALUE. Note: When VALUE is 0, Timer 0 counts to 1. AUX_TIMER0_EV pulses high for 1 peripheral clock period. Continuous Reload Mode: - Timer 0 increments until the counter value becomes equal to or greater than ( VALUE - 1), then restarts from 0. - AUX_TIMER0_EV pulses high for 1 peripheral clock period when the counter value is 0, except for when you enable the timer. Note: When VALUE is less than 2, Timer 0 counter value remains 0. AUX_TIMER0_EV goes high and remains high 1 peripheral clock period after you enable the timer. It is allowed to update the VALUE while the timer runs.

20.8.6.4 T0CNTR Register (Offset = Ch) [Reset = 00000000h]

T0CNTR is shown in #AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T0CNTR_FIGURE and described in #AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T0CNTR_TABLE.

Return to the Summary Table.

Timer 0 Counter

Figure 20-114 T0CNTR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																VALUE
R-0h																R-0h

Table 20-130 T0CNTR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	VALUE	R	0h	Timer 0 counter value.

20.8.6.5 T1CFG Register (Offset = 10h) [Reset = 00000000h]

T1CFG is shown in #AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T1CFG_FIGURE and described in #AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T1CFG_TABLE.

Return to the Summary Table.

Timer 1 Configuration

Figure 20-115 T1CFG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED	TICK_SRC_POL	TICK_SRC
R-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
PRE				RESERVED		MODE	RELOAD
R/W-0h				R-0h		R/W-0h	R/W-0h

Table 20-131 T1CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-15	RESERVED	R	0h	Reserved
14	TICK_SRC_POL	R/W	0h	Tick source polarity for Timer 1. 0h = Count on rising edges of TICK_SRC. 1h = Count on falling edges of TICK_SRC.
13-8	TICK_SRC	R/W	0h	Select Timer 1 tick source from the synchronous event bus. 0h = AUX_EVCTL:EVSTAT0.AUXIO0 1h = AUX_EVCTL:EVSTAT0.AUXIO1 2h = AUX_EVCTL:EVSTAT0.AUXIO2 3h = AUX_EVCTL:EVSTAT0.AUXIO3 4h = AUX_EVCTL:EVSTAT0.AUXIO4 5h = AUX_EVCTL:EVSTAT0.AUXIO5 6h = AUX_EVCTL:EVSTAT0.AUXIO6 7h = AUX_EVCTL:EVSTAT0.AUXIO7 8h = AUX_EVCTL:EVSTAT0.AUXIO8 9h = AUX_EVCTL:EVSTAT0.AUXIO9 Ah = AUX_EVCTL:EVSTAT0.AUXIO10 Bh = AUX_EVCTL:EVSTAT0.AUXIO11 Ch = AUX_EVCTL:EVSTAT0.AUXIO12 Dh = AUX_EVCTL:EVSTAT0.AUXIO13 Eh = AUX_EVCTL:EVSTAT0.AUXIO14 Fh = AUX_EVCTL:EVSTAT0.AUXIO15 10h = AUX_EVCTL:EVSTAT1.AUXIO16 11h = AUX_EVCTL:EVSTAT1.AUXIO17 12h = AUX_EVCTL:EVSTAT1.AUXIO18 13h = AUX_EVCTL:EVSTAT1.AUXIO19 14h = AUX_EVCTL:EVSTAT1.AUXIO20 15h = AUX_EVCTL:EVSTAT1.AUXIO21 16h = AUX_EVCTL:EVSTAT1.AUXIO22 17h = AUX_EVCTL:EVSTAT1.AUXIO23 18h = AUX_EVCTL:EVSTAT1.AUXIO24 19h = AUX_EVCTL:EVSTAT1.AUXIO25 1Ah = AUX_EVCTL:EVSTAT1.AUXIO26 1Bh = AUX_EVCTL:EVSTAT1.AUXIO27 1Ch = AUX_EVCTL:EVSTAT1.AUXIO28 1Dh = AUX_EVCTL:EVSTAT1.AUXIO29 1Eh = AUX_EVCTL:EVSTAT1.AUXIO30 1Fh = AUX_EVCTL:EVSTAT1.AUXIO31 20h = AUX_EVCTL:EVSTAT2.MANUAL_EV 21h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2 22h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY 23h = AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ 24h = AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD 25h = AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD 26h = AUX_EVCTL:EVSTAT2.SCLK_LF 27h = AUX_EVCTL:EVSTAT2.PWR_DWN 28h = AUX_EVCTL:EVSTAT2.MCU_ACTIVE 29h = AUX_EVCTL:EVSTAT2.VDDR_RECHARGE 2Ah = AUX_EVCTL:EVSTAT2.ACLK_REF 2Bh = AUX_EVCTL:EVSTAT2.MCU_EV 2Ch = AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 2Dh = AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 2Eh = AUX_EVCTL:EVSTAT2.AUX_COMPA 2Fh = AUX_EVCTL:EVSTAT2.AUX_COMPB 30h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 31h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 32h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 33h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 34h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE 35h = No event. 36h = AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV 37h = AUX_EVCTL:EVSTAT3.AUX_TDC_DONE 38h = AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N 39h = AUX_EVCTL:EVSTAT3.AUX_ADC_DONE 3Ah = AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ 3Bh = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL 3Ch = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY 3Dh = AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE 3Eh = AUX_EVCTL:EVSTAT3.AUX_DAC_HOLD_ACTIVE 3Fh = AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY
7-4	PRE	R/W	0h	Prescaler division ratio is 2^PRE: 0x0: Divide by 1. 0x1: Divide by 2. 0x2: Divide by 4. ... 0xF: Divide by 32,768.
3-2	RESERVED	R	0h	Reserved
1	MODE	R/W	0h	Timer 1 mode. Configure source for Timer 1 prescaler. 0h = Use clock as source for prescaler. Note that AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the clock frequency. 1h = Use event set by TICK_SRC as source for prescaler.
0	RELOAD	R/W	0h	Timer 1 reload mode. 0h = Manual mode. Timer 1 stops and T1CTL.EN becomes 0 when the counter value becomes equal to or greater than T1TARGET.VALUE. 1h = Continuous mode. Timer 1 restarts when the counter value becomes equal to or greater than ( T1TARGET.VALUE - 1).

20.8.6.6 T1CTL Register (Offset = 14h) [Reset = 00000000h]

T1CTL is shown in #AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T1CTL_FIGURE and described in #AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T1CTL_TABLE.

Return to the Summary Table.

Timer 1 Control

Figure 20-116 T1CTL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															EN
R-0h															R/W-0h

Table 20-132 T1CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	EN	R/W	0h	Timer 1 enable. 0: Disable Timer 1. 1: Enable Timer 1. The counter restarts from 0 when you enable Timer 1.

20.8.6.7 T1TARGET Register (Offset = 18h) [Reset = 00000000h]

T1TARGET is shown in #AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T1TARGET_FIGURE and described in #AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T1TARGET_TABLE.

Return to the Summary Table.

Timer 1 Target
Timer 1 counter target value

Figure 20-117 T1TARGET Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																VALUE
R-0h																R/W-0h

Table 20-133 T1TARGET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	VALUE	R/W	0h	Timer 1 target value. Manual Reload Mode: - Timer 1 increments until the counter value becomes equal to or greater than VALUE. - AUX_TIMER1_EV pulses high for 1 peripheral clock period when the counter value is equal to or greater than VALUE. Note: When VALUE is 0, Timer 1 counts to 1. AUX_TIMER1_EV pulses high for 1 peripheral clock period. Continuous Reload Mode: - Timer 1 increments until the counter value becomes equal to or greater than ( VALUE - 1), then restarts from 0. - AUX_TIMER1_EV pulses high for 1 peripheral clock period when the counter value is 0, except for when you enable the timer. Note: When VALUE is less than 2, Timer 1 counter value remains 0. AUX_TIMER1_EV goes high and remains high 1 peripheral clock period after you enable the timer. It is allowed to update the VALUE while the timer runs.

20.8.6.8 T1CNTR Register (Offset = 1Ch) [Reset = 00000000h]

T1CNTR is shown in #AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T1CNTR_FIGURE and described in #AUX_TIMER01_AUX_TIMER01_MMAP_AUX_TIMER01_AUX_TIMER01_ALL_T1CNTR_TABLE.

Return to the Summary Table.

Timer 1 Counter

Figure 20-118 T1CNTR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																VALUE
R-0h																R-0h

Table 20-134 T1CNTR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	VALUE	R	0h	Timer 1 counter value.