SWCU192 User guide | 德州仪器 TI.com.cn

SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

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43
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3. 46
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4. 53
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5. 58
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    21. 81
6. 82
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7. 86
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      1. 91
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    5. 96
    6. 97
      1. 98
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      3. 100
    7. 101
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    1. 103
      1. 104
8. 105
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9. 109
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115
1. 116
117
1. 118
2. 119
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    1. 122
    2. 123
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129
1. 130
  1. 131
  2. 132
  3. 133
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  5. 135
  6. 136
  7. 137
    1. 138
    2. 139
2. 140
  1. 141
  2. 142
  3. 143
  4. 144
3. 145
  1. 146
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    1. 148
4. 149
  1. 150
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    1. 152
    2. 153
    3. 154
5. 155
  1. 156
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    1. 158
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    3. 160
6. 161
7. 162
  1. 163
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165
1. 166
2. 167
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    1. 169
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    1. 171
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    3. 173
3. 174
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    5. 183
    6. 184
    7. 185
    8. 186
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  4. 188
    1. 189
      1. 190
      2. 191
      3. 192
    2. 193
      1. 194
    3. 195
      1. 196
4. 197
5. 198
6. 199
7. 200
8. 201
9. 202
10. 203
204
1. 205
2. 206
3. 207
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4. 209
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    1. 213
5. 214
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    3. 220
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6. 222
  1. 223
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  3. 225
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  5. 227
7. 228
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    1. 230
    2. 231
    3. 232
  2. 233
  3. 234
8. 235
  1. 236
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  3. 238
239
1. 240
2. 241
  1. 242
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    3. 245
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  4. 248
3. 249
  1. 250
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    1. 252
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    3. 254
4. 255
5. 256
  1. 257
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  3. 259
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6. 261
7. 262
  1. 263
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265
1. 266
2. 267
3. 268
4. 269
5. 270
6. 271
7. 272
  1. 273
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275
1. 276
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2. 279
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    1. 281
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    1. 283
      1. 284
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  3. 286
    1. 287
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    3. 289
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    13. 299
300
1. 301
2. 302
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3. 304
4. 305
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307
1. 308
2. 309
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3. 312
4. 313
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5. 317
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  3. 320
    1. 321
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      1. 325
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      1. 327
    3. 328
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    1. 330
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    1. 336
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6. 341
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7. 344
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  3. 350
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    2. 352
      1. 353
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      3. 355
    3. 356
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  4. 361
    1. 362
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      1. 364
    3. 365
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      3. 368
      4. 369
    4. 370
      1. 371
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    1. 377
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    3. 379
      1. 380
      2. 381
        
        382
      3.        383
        
                384
        
                385
        
                 386
        
                 387
        
                 388
        
                 389
        
                 390
        
                 391
        
                 392
        
                 393
        
                394
        
                395
        
                396
8. 397
  1. 398
    1. 399
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9. 402
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404
1. 405
2. 406
3. 407
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4. 412
  1. 413
5. 414
6. 415
7. 416
8. 417
9. 418
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    1. 420
    2. 421
10. 422
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426
1. 427
2. 428
3. 429
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4. 448
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    1. 451
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    3. 453
5. 454
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456
1. 457
2. 458
3. 459
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    1. 462
    2. 463
    3. 464
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    5. 466
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4. 469
  1. 470
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5. 475
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477
1. 478
2. 479
  1. 480
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  3. 482
    1. 483
  4. 484
3. 485
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4. 489
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491
1. 492
2. 493
3. 494
4. 495
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497
1. 498
2. 499
3. 500
4. 501
5. 502
  1. 503
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6. 506
  1. 507
    1. 508
    2. 509
    3. 510
      1. 511
      2. 512
7. 513
  1. 514
515
1. 516
  1. 517
2. 518
  1. 519
    1. 520
  2. 521
    1. 522
    2. 523
  3. 524
  4. 525
3. 526
  1. 527
    1. 528
    2. 529
    3. 530
    4. 531
  2. 532
    1. 533
      1. 534
    2. 535
      1. 536
      2. 537
    3. 538
      1. 539
    4. 540
      1. 541
      2. 542
      3. 543
    5. 544
    6. 545
    7. 546
    8. 547
    9. 548
    10. 549
4. 550
  1. 551
    1. 552
  2. 553
    1. 554
    2. 555
      1. 556
      2. 557
      3. 558
      4. 559
      5. 560
  3. 561
    1. 562
    2. 563
    3. 564
  4. 565
    1. 566
    2. 567
      1. 568
      2. 569
      3. 570
  5. 571
    1. 572
    2. 573
      1. 574
      2. 575
      3. 576
      4.        577
        
                578
        
                579
      5. 580
      6. 581
    3. 582
      1. 583
      2. 584
      3.        585
        
                586
        
                587
        
                588
        
                589
      4. 590
  6. 591
    1. 592
    2. 593
  7. 594
    1. 595
    2. 596
      1. 597
      2. 598
      3. 599
      4. 600
      5.        601
        
                602
        
                 603
        
                604
        
                 605
        
                606
        
                 607
      6. 608
5. 609
  1. 610
    1. 611
    2. 612
  2. 613
    1. 614
    2. 615
      1. 616
      2. 617
      3. 618
      4. 619
      5. 620
      6. 621
      7. 622
      8. 623
  3. 624
    1. 625
    2. 626
      1. 627
      2. 628
      3. 629
      4. 630
  4. 631
    1. 632
    2. 633
      1. 634
      2. 635
      3.        636
        
                637
        
                638
  5. 639
    1. 640
    2. 641
      1. 642
      2. 643
      3.        644
        
                645
        
                646
        
                647
      4.        648
        
                649
        
                650
        
                651
        
                652
      5. 653
      6. 654
  6. 655
    1. 656
    2. 657
      1. 658
      2. 659
      3. 660
      4. 661
      5. 662
6. 663
  1. 664
    1. 665
    2. 666
      1.        667
        
                668
        
                669
  2. 670
  3. 671
  4. 672
  5. 673
  6. 674
  7. 675
7. 676
8. 677
  1. 678
  2. 679
  3. 680
  4. 681
  5. 682
  6. 683
  7. 684
  8. 685
  9. 686
  10. 687
  11. 688
  12. 689
690
1. 691
2. 692
3. 693
  1. 694
695
1. 696
2. 697
3. 698
4. 699
  1. 700
  2. 701
  3. 702
  4. 703
    1. 704
    2. 705
      1. 706
      2. 707
  5. 708
  6. 709
  7. 710
5. 711
6. 712
7. 713
  1. 714
715
1. 716
2. 717
3. 718
4. 719
  1. 720
  2. 721
    1. 722
    2. 723
  3. 724
  4. 725
    1. 726
    2. 727
      1. 728
      2. 729
    3. 730
    4. 731
    5. 732
    6. 733
    7. 734
5. 735
6. 736
7. 737
  1. 738
739
1. 740
2. 741
3. 742
  1. 743
    1. 744
    2. 745
    3. 746
    4. 747
    5. 748
  2. 749
    1. 750
  3. 751
    1. 752
    2. 753
  4. 754
  5. 755
    1. 756
    2. 757
4. 758
5. 759
  1. 760
761
1. 762
2. 763
3. 764
4. 765
  1. 766
    1. 767
  2. 768
  3. 769
  4. 770
    1. 771
  5. 772
    1. 773
  6. 774
    1. 775
  7. 776
    1. 777
  8. 778
    1. 779
    2. 780
5. 781
  1. 782
  2. 783
  3. 784
  4. 785
    1. 786
    2. 787
    3. 788
6. 789
  1. 790
  2. 791
  3. 792
  4. 793
7. 794
8. 795
  1. 796
  2. 797
9. 798
  1. 799
800
1. 801
  1. 802
2. 803
  1. 804
  2. 805
  3. 806
    1. 807
    2. 808
    3. 809
  4. 810
    1. 811
    2. 812
    3. 813
3. 814
  1. 815
  2. 816
    1. 817
    2. 818
    3. 819
    4. 820
    5. 821
      1. 822
      2. 823
      3. 824
    6. 825
      1. 826
    7. 827
      1. 828
      2. 829
      3. 830
      4. 831
    8. 832
  3. 833
    1. 834
      1. 835
      2. 836
      3. 837
      4. 838
      5. 839
      6. 840
      7. 841
      8. 842
      9. 843
      10. 844
      11. 845
      12. 846
      13. 847
      14. 848
    2. 849
      1. 850
      2. 851
      3. 852
      4. 853
      5. 854
      6. 855
      7. 856
      8. 857
      9. 858
      10. 859
      11. 860
      12. 861
      13. 862
      14. 863
      15. 864
      16. 865
      17. 866
      18. 867
      19. 868
      20. 869
  4. 870
    1. 871
    2. 872
    3. 873
    4. 874
    5. 875
4. 876
  1. 877
    1. 878
    2. 879
    3. 880
    4. 881
    5. 882
  2. 883
    1. 884
    2. 885
5. 886
  1. 887
    1. 888
    2. 889
    3. 890
    4. 891
  2. 892
  3. 893
    1. 894
    2. 895
  4. 896
    1. 897
      1.        898
        
                899
        
                900
      2. 901
      3. 902
      4. 903
      5. 904
    2. 905
    3. 906
    4. 907
    5. 908
    6. 909
  5. 910
    1. 911
    2. 912
    3. 913
    4. 914
    5. 915
    6. 916
6. 917
  1. 918
    1. 919
      1. 920
    2. 921
    3. 922
    4. 923
  2. 924
7. 925
  1. 926
  2. 927
8. 928
  1. 929
  2. 930
  3. 931
  4. 932
  5. 933
  6. 934
  7. 935
  8. 936
    1. 937
    2. 938
    3. 939
    4. 940
  9. 941
    1. 942
    2. 943
    3. 944
  10. 945
    1. 946
    2. 947
    3. 948
    4. 949
    5. 950
  11. 951
    1. 952
    2. 953
    3. 954
    4. 955
    5. 956
  12. 957
  13. 958
  14. 959
  15. 960
  16. 961
  17. 962
9. 963
  1. 964
10. 965
  1. 966
  2. 967
    1. 968
      1. 969
    2. 970
    3. 971
  3. 972
  4. 973
    1. 974
    2. 975
  5. 976
    1. 977
    2. 978
      1. 979
    3. 980
      1. 981
      2. 982
    4. 983
      1. 984
      2. 985
    5. 986
      1. 987
      2. 988
      3. 989
  6. 990
    1. 991
    2. 992
11. 993
  1. 994
  2. 995
  3. 996
997

6.7.2 EVENT_FABRIC Registers

#EVENT_FABRIC_EVENT_FABRIC_MAP1_TABLE_1 lists the memory-mapped registers for the EVENT_FABRIC registers. All register offset addresses not listed in #EVENT_FABRIC_EVENT_FABRIC_MAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 6-14 EVENT_FABRIC Registers

Offset	Acronym	Register Name	Section
0h	CPUIRQSEL0	Output Selection for CPU Interrupt 0	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL0
4h	CPUIRQSEL1	Output Selection for CPU Interrupt 1	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL1
8h	CPUIRQSEL2	Output Selection for CPU Interrupt 2	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL2
Ch	CPUIRQSEL3	Output Selection for CPU Interrupt 3	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL3
10h	CPUIRQSEL4	Output Selection for CPU Interrupt 4	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL4
14h	CPUIRQSEL5	Output Selection for CPU Interrupt 5	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL5
18h	CPUIRQSEL6	Output Selection for CPU Interrupt 6	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL6
1Ch	CPUIRQSEL7	Output Selection for CPU Interrupt 7	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL7
20h	CPUIRQSEL8	Output Selection for CPU Interrupt 8	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL8
24h	CPUIRQSEL9	Output Selection for CPU Interrupt 9	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL9
28h	CPUIRQSEL10	Output Selection for CPU Interrupt 10	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL10
2Ch	CPUIRQSEL11	Output Selection for CPU Interrupt 11	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL11
30h	CPUIRQSEL12	Output Selection for CPU Interrupt 12	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL12
34h	CPUIRQSEL13	Output Selection for CPU Interrupt 13	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL13
38h	CPUIRQSEL14	Output Selection for CPU Interrupt 14	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL14
3Ch	CPUIRQSEL15	Output Selection for CPU Interrupt 15	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL15
40h	CPUIRQSEL16	Output Selection for CPU Interrupt 16	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL16
44h	CPUIRQSEL17	Output Selection for CPU Interrupt 17	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL17
48h	CPUIRQSEL18	Output Selection for CPU Interrupt 18	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL18
4Ch	CPUIRQSEL19	Output Selection for CPU Interrupt 19	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL19
50h	CPUIRQSEL20	Output Selection for CPU Interrupt 20	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL20
54h	CPUIRQSEL21	Output Selection for CPU Interrupt 21	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL21
58h	CPUIRQSEL22	Output Selection for CPU Interrupt 22	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL22
5Ch	CPUIRQSEL23	Output Selection for CPU Interrupt 23	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL23
60h	CPUIRQSEL24	Output Selection for CPU Interrupt 24	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL24
64h	CPUIRQSEL25	Output Selection for CPU Interrupt 25	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL25
68h	CPUIRQSEL26	Output Selection for CPU Interrupt 26	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL26
6Ch	CPUIRQSEL27	Output Selection for CPU Interrupt 27	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL27
70h	CPUIRQSEL28	Output Selection for CPU Interrupt 28	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL28
74h	CPUIRQSEL29	Output Selection for CPU Interrupt 29	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL29
78h	CPUIRQSEL30	Output Selection for CPU Interrupt 30	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL30
7Ch	CPUIRQSEL31	Output Selection for CPU Interrupt 31	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL31
80h	CPUIRQSEL32	Output Selection for CPU Interrupt 32	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL32
84h	CPUIRQSEL33	Output Selection for CPU Interrupt 33	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL33
88h	CPUIRQSEL34	Output Selection for CPU Interrupt 34	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL34
8Ch	CPUIRQSEL35	Output Selection for CPU Interrupt 35	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL35
90h	CPUIRQSEL36	Output Selection for CPU Interrupt 36	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL36
94h	CPUIRQSEL37	Output Selection for CPU Interrupt 37	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL37
100h	RFCSEL0	Output Selection for RFC Event 0	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL0
104h	RFCSEL1	Output Selection for RFC Event 1	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL1
108h	RFCSEL2	Output Selection for RFC Event 2	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL2
10Ch	RFCSEL3	Output Selection for RFC Event 3	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL3
110h	RFCSEL4	Output Selection for RFC Event 4	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL4
114h	RFCSEL5	Output Selection for RFC Event 5	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL5
118h	RFCSEL6	Output Selection for RFC Event 6	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL6
11Ch	RFCSEL7	Output Selection for RFC Event 7	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL7
120h	RFCSEL8	Output Selection for RFC Event 8	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL8
124h	RFCSEL9	Output Selection for RFC Event 9	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL9
200h	GPT0ACAPTSEL	Output Selection for GPT0 0	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_GPT0ACAPTSEL
204h	GPT0BCAPTSEL	Output Selection for GPT0 1	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_GPT0BCAPTSEL
300h	GPT1ACAPTSEL	Output Selection for GPT1 0	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_GPT1ACAPTSEL
304h	GPT1BCAPTSEL	Output Selection for GPT1 1	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_GPT1BCAPTSEL
400h	GPT2ACAPTSEL	Output Selection for GPT2 0	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_GPT2ACAPTSEL
404h	GPT2BCAPTSEL	Output Selection for GPT2 1	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_GPT2BCAPTSEL
508h	UDMACH1SSEL	Output Selection for DMA Channel 1 SREQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH1SSEL
50Ch	UDMACH1BSEL	Output Selection for DMA Channel 1 REQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH1BSEL
510h	UDMACH2SSEL	Output Selection for DMA Channel 2 SREQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH2SSEL
514h	UDMACH2BSEL	Output Selection for DMA Channel 2 REQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH2BSEL
518h	UDMACH3SSEL	Output Selection for DMA Channel 3 SREQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH3SSEL
51Ch	UDMACH3BSEL	Output Selection for DMA Channel 3 REQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH3BSEL
520h	UDMACH4SSEL	Output Selection for DMA Channel 4 SREQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH4SSEL
524h	UDMACH4BSEL	Output Selection for DMA Channel 4 REQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH4BSEL
528h	UDMACH5SSEL	Output Selection for DMA Channel 5 SREQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH5SSEL
52Ch	UDMACH5BSEL	Output Selection for DMA Channel 5 REQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH5BSEL
530h	UDMACH6SSEL	Output Selection for DMA Channel 6 SREQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH6SSEL
534h	UDMACH6BSEL	Output Selection for DMA Channel 6 REQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH6BSEL
538h	UDMACH7SSEL	Output Selection for DMA Channel 7 SREQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH7SSEL
53Ch	UDMACH7BSEL	Output Selection for DMA Channel 7 REQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH7BSEL
540h	UDMACH8SSEL	Output Selection for DMA Channel 8 SREQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH8SSEL
544h	UDMACH8BSEL	Output Selection for DMA Channel 8 REQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH8BSEL
548h	UDMACH9SSEL	Output Selection for DMA Channel 9 SREQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH9SSEL
54Ch	UDMACH9BSEL	Output Selection for DMA Channel 9 REQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH9BSEL
550h	UDMACH10SSEL	Output Selection for DMA Channel 10 SREQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH10SSEL
554h	UDMACH10BSEL	Output Selection for DMA Channel 10 REQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH10BSEL
558h	UDMACH11SSEL	Output Selection for DMA Channel 11 SREQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH11SSEL
55Ch	UDMACH11BSEL	Output Selection for DMA Channel 11 REQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH11BSEL
560h	UDMACH12SSEL	Output Selection for DMA Channel 12 SREQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH12SSEL
564h	UDMACH12BSEL	Output Selection for DMA Channel 12 REQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH12BSEL
56Ch	UDMACH13BSEL	Output Selection for DMA Channel 13 REQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH13BSEL
574h	UDMACH14BSEL	Output Selection for DMA Channel 14 REQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH14BSEL
57Ch	UDMACH15BSEL	Output Selection for DMA Channel 15 REQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH15BSEL
580h	UDMACH16SSEL	Output Selection for DMA Channel 16 SREQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH16SSEL
584h	UDMACH16BSEL	Output Selection for DMA Channel 16 REQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH16BSEL
588h	UDMACH17SSEL	Output Selection for DMA Channel 17 SREQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH17SSEL
58Ch	UDMACH17BSEL	Output Selection for DMA Channel 17 REQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH17BSEL
5A8h	UDMACH21SSEL	Output Selection for DMA Channel 21 SREQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH21SSEL
5ACh	UDMACH21BSEL	Output Selection for DMA Channel 21 REQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH21BSEL
5B0h	UDMACH22SSEL	Output Selection for DMA Channel 22 SREQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH22SSEL
5B4h	UDMACH22BSEL	Output Selection for DMA Channel 22 REQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH22BSEL
5B8h	UDMACH23SSEL	Output Selection for DMA Channel 23 SREQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH23SSEL
5BCh	UDMACH23BSEL	Output Selection for DMA Channel 23 REQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH23BSEL
5C0h	UDMACH24SSEL	Output Selection for DMA Channel 24 SREQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH24SSEL
5C4h	UDMACH24BSEL	Output Selection for DMA Channel 24 REQ	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_UDMACH24BSEL
600h	GPT3ACAPTSEL	Output Selection for GPT3 0	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_GPT3ACAPTSEL
604h	GPT3BCAPTSEL	Output Selection for GPT3 1	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_GPT3BCAPTSEL
700h	AUXSEL0	Output Selection for AUX Subscriber 0	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_AUXSEL0
800h	CM3NMISEL0	Output Selection for NMI Subscriber 0	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CM3NMISEL0
900h	I2SSTMPSEL0	Output Selection for I2S Subscriber 0	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_I2SSTMPSEL0
A00h	FRZSEL0	Output Selection for FRZ Subscriber	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_FRZSEL0
F00h	SWEV	Set or Clear Software Events	#EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_SWEV

Complex bit access types are encoded to fit into small table cells. #EVENT_FABRIC_EVENT_FABRIC_MAP1_LEGEND shows the codes that are used for access types in this section.

Table 6-15 EVENT_FABRIC Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

6.7.2.1 CPUIRQSEL0 Register (Offset = 0h) [Reset = 00000004h]

CPUIRQSEL0 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL0_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL0_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 0

Figure 6-10 CPUIRQSEL0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-4h

Table 6-16 CPUIRQSEL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	4h	Read only selection value 4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings

6.7.2.2 CPUIRQSEL1 Register (Offset = 4h) [Reset = 00000009h]

CPUIRQSEL1 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL1_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL1_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 1

Figure 6-11 CPUIRQSEL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-9h

Table 6-17 CPUIRQSEL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	9h	Read only selection value 9h = Interrupt event from I2C

6.7.2.3 CPUIRQSEL2 Register (Offset = 8h) [Reset = 0000001Eh]

CPUIRQSEL2 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL2_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL2_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 2

Figure 6-12 CPUIRQSEL2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-1Eh

Table 6-18 CPUIRQSEL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	1Eh	Read only selection value 1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event

6.7.2.4 CPUIRQSEL3 Register (Offset = Ch) [Reset = 0000001Fh]

CPUIRQSEL3 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL3_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL3_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 3

Figure 6-13 CPUIRQSEL3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-1Fh

Table 6-19 CPUIRQSEL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	1Fh	Read only selection value 1Fh = PKA Interrupt event

6.7.2.5 CPUIRQSEL4 Register (Offset = 10h) [Reset = 00000007h]

CPUIRQSEL4 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL4_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL4_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 4

Figure 6-14 CPUIRQSEL4 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-7h

Table 6-20 CPUIRQSEL4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	7h	Read only selection value 7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting

6.7.2.6 CPUIRQSEL5 Register (Offset = 14h) [Reset = 00000024h]

CPUIRQSEL5 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL5_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL5_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 5

Figure 6-15 CPUIRQSEL5 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-24h

Table 6-21 CPUIRQSEL5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	24h	Read only selection value 24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS

6.7.2.7 CPUIRQSEL6 Register (Offset = 18h) [Reset = 0000001Ch]

CPUIRQSEL6 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL6_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL6_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 6

Figure 6-16 CPUIRQSEL6 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-1Ch

Table 6-22 CPUIRQSEL6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	1Ch	Read only selection value 1Ch = AUX software event 0, triggered by AUX_EVCTL:SWEVSET.SWEV0, also available as AUX_EVENT0 AON wake up event. MCU domain wakeup control AON_EVENT:MCUWUSEL

6.7.2.8 CPUIRQSEL7 Register (Offset = 1Ch) [Reset = 00000022h]

CPUIRQSEL7 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL7_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL7_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 7

Figure 6-17 CPUIRQSEL7 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-22h

Table 6-23 CPUIRQSEL7 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	22h	Read only selection value 22h = SSI0 combined interrupt, interrupt flags are found here SSI0:MIS

6.7.2.9 CPUIRQSEL8 Register (Offset = 20h) [Reset = 00000023h]

CPUIRQSEL8 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL8_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL8_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 8

Figure 6-18 CPUIRQSEL8 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-23h

Table 6-24 CPUIRQSEL8 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	23h	Read only selection value 23h = SSI1 combined interrupt, interrupt flags are found here SSI1:MIS

6.7.2.10 CPUIRQSEL9 Register (Offset = 24h) [Reset = 0000001Bh]

CPUIRQSEL9 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL9_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL9_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 9

Figure 6-19 CPUIRQSEL9 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-1Bh

Table 6-25 CPUIRQSEL9 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	1Bh	Read only selection value 1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event

6.7.2.11 CPUIRQSEL10 Register (Offset = 28h) [Reset = 0000001Ah]

CPUIRQSEL10 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL10_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL10_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 10

Figure 6-20 CPUIRQSEL10 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-1Ah

Table 6-26 CPUIRQSEL10 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	1Ah	Read only selection value 1Ah = Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG

6.7.2.12 CPUIRQSEL11 Register (Offset = 2Ch) [Reset = 00000019h]

CPUIRQSEL11 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL11_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL11_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 11

Figure 6-21 CPUIRQSEL11 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-19h

Table 6-27 CPUIRQSEL11 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	19h	Read only selection value 19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG

6.7.2.13 CPUIRQSEL12 Register (Offset = 30h) [Reset = 00000008h]

CPUIRQSEL12 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL12_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL12_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 12

Figure 6-22 CPUIRQSEL12 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-8h

Table 6-28 CPUIRQSEL12 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	8h	Read only selection value 8h = Interrupt event from I2S

6.7.2.14 CPUIRQSEL13 Register (Offset = 34h) [Reset = 0000001Dh]

CPUIRQSEL13 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL13_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL13_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 13

Figure 6-23 CPUIRQSEL13 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-1Dh

Table 6-29 CPUIRQSEL13 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	1Dh	Read only selection value 1Dh = AUX software event 1, triggered by AUX_EVCTL:SWEVSET.SWEV1, also available as AUX_EVENT2 AON wake up event. MCU domain wakeup control AON_EVENT:MCUWUSEL

6.7.2.15 CPUIRQSEL14 Register (Offset = 38h) [Reset = 00000018h]

CPUIRQSEL14 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL14_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL14_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 14

Figure 6-24 CPUIRQSEL14 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-18h

Table 6-30 CPUIRQSEL14 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	18h	Read only selection value 18h = Watchdog interrupt event, controlled by WDT:CTL.INTEN

6.7.2.16 CPUIRQSEL15 Register (Offset = 3Ch) [Reset = 00000010h]

CPUIRQSEL15 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL15_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL15_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 15

Figure 6-25 CPUIRQSEL15 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-10h

Table 6-31 CPUIRQSEL15 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	10h	Read only selection value 10h = GPT0A interrupt event, controlled by GPT0:TAMR

6.7.2.17 CPUIRQSEL16 Register (Offset = 40h) [Reset = 00000011h]

CPUIRQSEL16 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL16_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL16_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 16

Figure 6-26 CPUIRQSEL16 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-11h

Table 6-32 CPUIRQSEL16 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	11h	Read only selection value 11h = GPT0B interrupt event, controlled by GPT0:TBMR

6.7.2.18 CPUIRQSEL17 Register (Offset = 44h) [Reset = 00000012h]

CPUIRQSEL17 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL17_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL17_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 17

Figure 6-27 CPUIRQSEL17 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-12h

Table 6-33 CPUIRQSEL17 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	12h	Read only selection value 12h = GPT1A interrupt event, controlled by GPT1:TAMR

6.7.2.19 CPUIRQSEL18 Register (Offset = 48h) [Reset = 00000013h]

CPUIRQSEL18 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL18_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL18_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 18

Figure 6-28 CPUIRQSEL18 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-13h

Table 6-34 CPUIRQSEL18 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	13h	Read only selection value 13h = GPT1B interrupt event, controlled by GPT1:TBMR

6.7.2.20 CPUIRQSEL19 Register (Offset = 4Ch) [Reset = 0000000Ch]

CPUIRQSEL19 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL19_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL19_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 19

Figure 6-29 CPUIRQSEL19 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-Ch

Table 6-35 CPUIRQSEL19 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	Ch	Read only selection value Ch = GPT2A interrupt event, controlled by GPT2:TAMR

6.7.2.21 CPUIRQSEL20 Register (Offset = 50h) [Reset = 0000000Dh]

CPUIRQSEL20 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL20_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL20_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 20

Figure 6-30 CPUIRQSEL20 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-Dh

Table 6-36 CPUIRQSEL20 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	Dh	Read only selection value Dh = GPT2B interrupt event, controlled by GPT2:TBMR

6.7.2.22 CPUIRQSEL21 Register (Offset = 54h) [Reset = 0000000Eh]

CPUIRQSEL21 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL21_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL21_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 21

Figure 6-31 CPUIRQSEL21 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-Eh

Table 6-37 CPUIRQSEL21 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	Eh	Read only selection value Eh = GPT3A interrupt event, controlled by GPT3:TAMR

6.7.2.23 CPUIRQSEL22 Register (Offset = 58h) [Reset = 0000000Fh]

CPUIRQSEL22 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL22_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL22_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 22

Figure 6-32 CPUIRQSEL22 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-Fh

Table 6-38 CPUIRQSEL22 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	Fh	Read only selection value Fh = GPT3B interrupt event, controlled by GPT3:TBMR

6.7.2.24 CPUIRQSEL23 Register (Offset = 5Ch) [Reset = 0000005Dh]

CPUIRQSEL23 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL23_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL23_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 23

Figure 6-33 CPUIRQSEL23 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-5Dh

Table 6-39 CPUIRQSEL23 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	5Dh	Read only selection value 5Dh = CRYPTO result available interupt event, the corresponding flag is found here CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by CRYPTO:IRQSTAT.RESULT_AVAIL

6.7.2.25 CPUIRQSEL24 Register (Offset = 60h) [Reset = 00000027h]

CPUIRQSEL24 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL24_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL24_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 24

Figure 6-34 CPUIRQSEL24 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-27h

Table 6-40 CPUIRQSEL24 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	27h	Read only selection value 27h = Combined DMA done, corresponding flags are here UDMA0:REQDONE

6.7.2.26 CPUIRQSEL25 Register (Offset = 64h) [Reset = 00000026h]

CPUIRQSEL25 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL25_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL25_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 25

Figure 6-35 CPUIRQSEL25 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-26h

Table 6-41 CPUIRQSEL25 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	26h	Read only selection value 26h = DMA bus error, corresponds to UDMA0:ERROR.STATUS

6.7.2.27 CPUIRQSEL26 Register (Offset = 68h) [Reset = 00000015h]

CPUIRQSEL26 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL26_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL26_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 26

Figure 6-36 CPUIRQSEL26 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-15h

Table 6-42 CPUIRQSEL26 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	15h	Read only selection value 15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT

6.7.2.28 CPUIRQSEL27 Register (Offset = 6Ch) [Reset = 00000064h]

CPUIRQSEL27 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL27_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL27_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 27

Figure 6-37 CPUIRQSEL27 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-64h

Table 6-43 CPUIRQSEL27 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	64h	Read only selection value 64h = Software event 0, triggered by SWEV.SWEV0

6.7.2.29 CPUIRQSEL28 Register (Offset = 70h) [Reset = 0000000Bh]

CPUIRQSEL28 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL28_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL28_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 28

Figure 6-38 CPUIRQSEL28 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-Bh

Table 6-44 CPUIRQSEL28 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	Bh	Read only selection value Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS

6.7.2.30 CPUIRQSEL29 Register (Offset = 74h) [Reset = 00000001h]

CPUIRQSEL29 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL29_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL29_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 29

Figure 6-39 CPUIRQSEL29 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-1h

Table 6-45 CPUIRQSEL29 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	1h	Read only selection value 1h = AON programmable event 0. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG0_EV

6.7.2.31 CPUIRQSEL30 Register (Offset = 78h) [Reset = 00000000h]

CPUIRQSEL30 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL30_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL30_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 30

Figure 6-40 CPUIRQSEL30 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R/W-0h

Table 6-46 CPUIRQSEL30 Register Field Descriptions

Bit

Field

Type

Reset

Description

31-7

RESERVED

Reserved

6-0

R/W

Read/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.

0h = Always inactive

2h = AON programmable event 1. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG1_EV

3h = AON programmable event 2. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG2_EV

8h = Interrupt event from I2S

Ah = AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0

14h = DMA done for software tiggered UDMA channel 0, see UDMA0:SOFTREQ

16h = DMA done for software tiggered UDMA channel 18, see UDMA0:SOFTREQ

38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0

39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1

3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2

3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3

3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE

5Eh = CRYPTO DMA input done event, the correspondingg flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled by CRYPTO:IRQEN.DMA_IN_DONE

69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV

6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB

6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE

6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV

6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV

6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE

70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE

71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL

72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0

77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN

79h = Always asserted

6.7.2.32 CPUIRQSEL31 Register (Offset = 7Ch) [Reset = 0000006Ah]

CPUIRQSEL31 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL31_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL31_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 31

Figure 6-41 CPUIRQSEL31 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-6Ah

Table 6-47 CPUIRQSEL31 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	6Ah	Read only selection value 6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA

6.7.2.33 CPUIRQSEL32 Register (Offset = 80h) [Reset = 00000073h]

CPUIRQSEL32 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL32_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL32_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 32

Figure 6-42 CPUIRQSEL32 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-73h

Table 6-48 CPUIRQSEL32 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	73h	Read only selection value 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS

6.7.2.34 CPUIRQSEL33 Register (Offset = 84h) [Reset = 00000068h]

CPUIRQSEL33 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL33_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL33_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 33

Figure 6-43 CPUIRQSEL33 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-68h

Table 6-49 CPUIRQSEL33 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	68h	Read only selection value 68h = TRNG Interrupt event, controlled by TRNG:IRQEN.EN

6.7.2.35 CPUIRQSEL34 Register (Offset = 88h) [Reset = 00000006h]

CPUIRQSEL34 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL34_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL34_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 34

Figure 6-44 CPUIRQSEL34 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-6h

Table 6-50 CPUIRQSEL34 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	6h	Read only selection value 6h = Combined event from Oscillator control

6.7.2.36 CPUIRQSEL35 Register (Offset = 8Ch) [Reset = 00000038h]

CPUIRQSEL35 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL35_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL35_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 35

Figure 6-45 CPUIRQSEL35 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-38h

Table 6-51 CPUIRQSEL35 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	38h	Read only selection value 38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0

6.7.2.37 CPUIRQSEL36 Register (Offset = 90h) [Reset = 00000025h]

CPUIRQSEL36 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL36_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL36_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 36

Figure 6-46 CPUIRQSEL36 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-25h

Table 6-52 CPUIRQSEL36 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	25h	Read only selection value 25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS

6.7.2.38 CPUIRQSEL37 Register (Offset = 94h) [Reset = 00000005h]

CPUIRQSEL37 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL37_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_CPUIRQSEL37_TABLE.

Return to the Summary Table.

Output Selection for CPU Interrupt 37

Figure 6-47 CPUIRQSEL37 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-5h

Table 6-53 CPUIRQSEL37 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	5h	Read only selection value 5h = Combined event from battery monitor

6.7.2.39 RFCSEL0 Register (Offset = 100h) [Reset = 0000003Dh]

RFCSEL0 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL0_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL0_TABLE.

Return to the Summary Table.

Output Selection for RFC Event 0

Figure 6-48 RFCSEL0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-3Dh

Table 6-54 RFCSEL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	3Dh	Read only selection value 3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT

6.7.2.40 RFCSEL1 Register (Offset = 104h) [Reset = 0000003Eh]

RFCSEL1 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL1_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL1_TABLE.

Return to the Summary Table.

Output Selection for RFC Event 1

Figure 6-49 RFCSEL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-3Eh

Table 6-55 RFCSEL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	3Eh	Read only selection value 3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT

6.7.2.41 RFCSEL2 Register (Offset = 108h) [Reset = 0000003Fh]

RFCSEL2 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL2_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL2_TABLE.

Return to the Summary Table.

Output Selection for RFC Event 2

Figure 6-50 RFCSEL2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-3Fh

Table 6-56 RFCSEL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	3Fh	Read only selection value 3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT

6.7.2.42 RFCSEL3 Register (Offset = 10Ch) [Reset = 00000040h]

RFCSEL3 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL3_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL3_TABLE.

Return to the Summary Table.

Output Selection for RFC Event 3

Figure 6-51 RFCSEL3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-40h

Table 6-57 RFCSEL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	40h	Read only selection value 40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT

6.7.2.43 RFCSEL4 Register (Offset = 110h) [Reset = 00000041h]

RFCSEL4 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL4_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL4_TABLE.

Return to the Summary Table.

Output Selection for RFC Event 4

Figure 6-52 RFCSEL4 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-41h

Table 6-58 RFCSEL4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	41h	Read only selection value 41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT

6.7.2.44 RFCSEL5 Register (Offset = 114h) [Reset = 00000042h]

RFCSEL5 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL5_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL5_TABLE.

Return to the Summary Table.

Output Selection for RFC Event 5

Figure 6-53 RFCSEL5 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-42h

Table 6-59 RFCSEL5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	42h	Read only selection value 42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT

6.7.2.45 RFCSEL6 Register (Offset = 118h) [Reset = 00000043h]

RFCSEL6 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL6_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL6_TABLE.

Return to the Summary Table.

Output Selection for RFC Event 6

Figure 6-54 RFCSEL6 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-43h

Table 6-60 RFCSEL6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	43h	Read only selection value 43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT

6.7.2.46 RFCSEL7 Register (Offset = 11Ch) [Reset = 00000044h]

RFCSEL7 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL7_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL7_TABLE.

Return to the Summary Table.

Output Selection for RFC Event 7

Figure 6-55 RFCSEL7 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-44h

Table 6-61 RFCSEL7 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	44h	Read only selection value 44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT

6.7.2.47 RFCSEL8 Register (Offset = 120h) [Reset = 00000077h]

RFCSEL8 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL8_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL8_TABLE.

Return to the Summary Table.

Output Selection for RFC Event 8

Figure 6-56 RFCSEL8 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R-77h

Table 6-62 RFCSEL8 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	EV	R	77h	Read only selection value 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN

6.7.2.48 RFCSEL9 Register (Offset = 124h) [Reset = 00000002h]

RFCSEL9 is shown in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL9_FIGURE and described in #EVENT_FABRIC_EVENT_FABRIC_MAP1_EVENT_FABRIC_ALL_RFCSEL9_TABLE.

Return to the Summary Table.

Output Selection for RFC Event 9

Figure 6-57 RFCSEL9 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									EV
R-0h																									R/W-2h

Table 6-63 RFCSEL9 Register Field Descriptions

Bit

Field

Type

Reset

Description

31-7

RESERVED

Reserved

6-0

R/W

Read/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.

0h = Always inactive

1h = AON programmable event 0. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG0_EV

2h = AON programmable event 1. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG1_EV

8h = Interrupt event from I2S

Ah = AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0

18h = Watchdog interrupt event, controlled by WDT:CTL.INTEN

22h = SSI0 combined interrupt, interrupt flags are found here SSI0:MIS

23h = SSI1 combined interrupt, interrupt flags are found here SSI1:MIS

24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS

25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS

27h = Combined DMA done, corresponding flags are here UDMA0:REQDONE

38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0

39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1

3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2

3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3

3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE

5Dh = CRYPTO result available interupt event, the corresponding flag is found here CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by CRYPTO:IRQSTAT.RESULT_AVAIL

64h = Software event 0, triggered by SWEV.SWEV0

65h = Software event 1, triggered by SWEV.SWEV1

69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV

6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA