SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
Table 3-27 lists the instruction set of the FPU.
| Operation | Description | Assembler | Cycles |
|---|---|---|---|
| Absolute value | of float | | 1 |
| Addition | floating point | | 1 |
| Compare | float with register or zero | | 1 |
| float with register or zero | | 1 | |
| Convert | between integer, fixed-point, half-precision and float | | 1 |
| Divide | Floating-point | | 14 |
| Load | multiple doubles | | 1 + 2 × N, where N is the number of doubles. |
| multiple floats | | 1 + N, where N is the number of floats. | |
| single double | | 3 | |
| single float | | 2 | |
| Move | top/bottom half of double to/from core register | | 1 |
| immediate/float to float-register | | 1 | |
| two floats/one double to/from two core registers or one float to/from one core register | | 2 | |
| floating-point control/status to core register | | 1 | |
| core register to floating-point control/status | | 1 | |
| Multiply | float | | 1 |
| then accumulate float | | 3 | |
| then subtract float | | 3 | |
| then accumulate then negate float | | 3 | |
| then subtract then negate float | | 3 | |
| Multiply (fused) | then accumulate float | | 3 |
| then subtract float | | 3 | |
| then accumulate then negate float | | 3 | |
| then subtract then negate float | | 3 | |
| Negate | float | | 1 |
| and multiply float | | 1 | |
| Pop | double registers from stack | | 1 + 2 × N, where N is the number of double registers |
| float registers from stack | | 1 + N, where N is the number of registers | |
| Push | double registers to stack | | 1 + 2 × N, where N is the number of double registers |
| float registers to stack | | 1 + N, where N is the number of registers | |
| Square-root | of float | | 14 |
| Store | multiple double registers | | 1 + 2 × N, where N is the number of doubles |
| multiple float registers | | 1 + N, where N is the number of floats | |
| single double register | | 3 | |
| single float registers | | 2 | |
| Subtract | float | | 1 |