SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The baud-rate divisor (BRD) is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional baud-rate divider allows the UART to generate all standard baud rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor Register (UART:IBRD), and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor Register (UART:FBRD). Equation 4 shows the relationship of the BRD and the system clock.
where:
The 6-bit fractional number that is loaded into the UART:FBRD DIVFRAC bit field can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to account for rounding errors, as shown by Equation 5.
Along with the UART Line Control, High Byte Register (UART:LCRH), the UART_IBRD and the UART:FBRD registers form an internal 30-bit register. This internal register is updated only when a write operation to the UART:LCRH register is performed, so a write to the UART:LCRH register must follow any changes to the BRD for the changes to take effect.
The four possible sequences to update the baud-rate registers are as follows: