SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The processor implements the ARMv7-M Thumb instruction set. Table 3-25 lists the Arm® Cortex®-M4F instructions and their cycle counts. The cycle counts are based on a system with zero wait states.
Within the assembler syntax, depending on the operation, the <op2> field can be replaced with one of the following options:
RmRm, LSL #4Rm, LSL Rs#0xE000E000For brevity, not all load and store addressing modes are shown. See the ARMv7-M Architecture Reference Manual for more information.
Table 3-25 uses the following abbreviations in the Cycles column:
| Operation | Description | Assembler | Cycles |
|---|---|---|---|
| Move | Register | | 1 |
| 16-bit immediate | | 1 | |
| Immediate into top | | 1 | |
| To PC | | 1 + P | |
| Add | Add | | 1 |
| Add to PC | | 1 + P | |
| Add with carry | | 1 | |
| Form address | | 1 | |
| Subtract | Subtract | | 1 |
| Subtract with borrow | | 1 | |
| Reverse | | 1 | |
| Multiply | Multiply | | 1 |
| Multiply accumulate | | 1 | |
| Multiply subtract | | 1 | |
| Long signed | | 1 | |
| Long unsigned | | 1 | |
| Long signed accumulate | | 1 | |
| Long unsigned accumulate | | 1 | |
| Divide | Signed | | 2 to 12(1) |
| Unsigned | | 2 to 12(1) | |
| Saturate | Signed | | 1 |
| Unsigned | | 1 | |
| Compare | Compare | | 1 |
| Negative | | 1 | |
| Logical | AND | | 1 |
| Exclusive OR | | 1 | |
| OR | | 1 | |
| OR NOT | | 1 | |
| Bit clear | | 1 | |
| Move NOT | | 1 | |
| AND test | | 1 | |
| Exclusive OR test | | 1 | |
| Shift | Logical shift left | | 1 |
| Logical shift left | | 1 | |
| Logical shift right | | 1 | |
| Logical shift right | | 1 | |
| Arithmetic shift right | | 1 | |
| Arithmetic shift right | | 1 | |
| Rotate | Rotate right | | 1 |
| Rotate right | | 1 | |
| With extension | | 1 | |
| Count | Leading zeroes | | 1 |
| Load | Word | | 2(2) |
| To PC | | 2(2) + P | |
| Halfword | | 2(2) | |
| Byte | | 2(2) | |
| Signed halfword | | 2(2) | |
| Signed byte | | 2(2) | |
| User word | | 2(2) | |
| User halfword | | 2(2) | |
| User byte | | 2(2) | |
| User signed halfword | | 2(2) | |
| User signed byte | | 2(2) | |
| PC relative | | 2(2) | |
| Doubleword | | 1 + N | |
| Multiple | | 1 + N | |
| Multiple including PC | | 1 + N + P | |
| Store | Word | | 2(2) |
| Halfword | | 2(2) | |
| Byte | | 2(2) | |
| Signed halfword | | 2(2) | |
| Signed byte | | 2(2) | |
| User word | | 2(2) | |
| User halfword | | 2(2) | |
| User byte | | 2(2) | |
| User signed halfword | | 2(2) | |
| User signed byte | | 2(2) | |
| Doubleword | | 1 + N | |
| Multiple | | 1 + N | |
| Push | Push | | 1 + N |
| Push with link register | | 1 + N | |
| Pop | Pop | | 1 + N |
| Pop and return | | 1 + N + P | |
| Semaphore | Load exclusive | | 2 |
| Load exclusive half | | 2 | |
| Load exclusive byte | | 2 | |
| Store exclusive | | 2 | |
| Store exclusive half | | 2 | |
| Store exclusive byte | | 2 | |
| Clear exclusive monitor | | 1 | |
| Branch | Conditional | | 1 or 1 + P(3) |
| Unconditional | | 1 + P | |
| With link | | 1 + P | |
| With exchange | | 1 + P | |
| With link and exchange | | 1 + P | |
| Branch if zero | | 1 or 1 + P(3) | |
| Branch if nonzero | | 1 or 1 + P(3) | |
| Byte table branch | | 2 + P | |
| Halfword table branch | | 2 + P | |
| State change | Supervisor call | | – |
| If-then-else | | 1(4) | |
| Disable interrupts | | 1 or 2 | |
| Enable interrupts | | 1 or 2 | |
| Read special register | | 1 or 2 | |
| Write special register | | 1 or 2 | |
| Breakpoint | | – | |
| Extend | Signed halfword to word | | 1 |
| Signed byte to word | | 1 | |
| Unsigned halfword | | 1 | |
| Unsigned byte | | 1 | |
| Bit field | Extract unsigned | | 1 |
| Extract signed | | 1 | |
| Clear | | 1 | |
| Insert | | 1 | |
| Reverse | Bytes in word | | 1 |
| Bytes in both halfwords | | 1 | |
| Signed bottom halfword | | 1 | |
| Bits in word | | 1 | |
| Hint | Send event | | 1 |
| Wait for event | | 1 + W | |
| Wait for interrupt | | 1 + W | |
| No operation | | 1 | |
| Barriers | Instruction synchronization | | 1 + B |
| Data memory | | 1 + B | |
| Data synchronization | | 1 + B |
Table 3-26 lists the DSP instructions that the Arm® Cortex®-M4F processor implements.
| Operation | Description | Assembler | Cycles |
|---|---|---|---|
| Multiply | 32 bit multiply with 32 most significant bit accumulate | | 1 |
| 32 bit multiply with 32 most significant bit subtract | | 1 | |
| 32 bit multiply returning 32 most significant bits | | 1 | |
| 32 bit multiply with rounded 32 most significant bit accumulate | | 1 | |
| 32 bit multiply with rounded 32 most significant bit subtract | | 1 | |
| 32 bit multiply returning rounded 32 most significant bits | | 1 | |
| Signed multiply | Q setting 16 bit signed multiply with 32 bit accumulate, bottom by bottom | | 1 |
| Q setting 16 bit signed multiply with 32 bit accumulate, bottom by top | | 1 | |
| 16 bit signed multiply with 64 bit accumulate, bottom by bottom | | 1 | |
| 16 bit signed multiply with 64 bit accumulate, bottom by top | | 1 | |
| Dual 16 bit signed multiply with single 64 bit accumulator | | 1 | |
| 16 bit signed multiply with 64 bit accumulate, top by bottom | | 1 | |
| 16 bit signed multiply with 64 bit accumulate, top by top | | 1 | |
| 16 bit signed multiply yielding 32 bit result, bottom by bottom | | 1 | |
| 16 bit signed multiply yielding 32 bit result, bottom by top | | 1 | |
| 16 bit signed multiply yielding 32 bit result, top by bottom | | 1 | |
| 16 bit signed multiply yielding 32 bit result, top by top | | 1 | |
| 16 bit by 32 bit signed multiply returning 32 most significant bits, bottom | | 1 | |
| 16 bit by 32 bit signed multiply returning 32 most significant bits, top | | 1 | |
| Dual 16 bit signed multiply returning difference | | 1 | |
| Q setting 16 bit signed multiply with 32 bit accumulate, top by bottom | | 1 | |
| Q setting 16 bit signed multiply with 32 bit accumulate, top by top | | 1 | |
| Q setting dual 16 bit signed multiply with single 32 bit accumulator | | 1 | |
| Q setting 16 bit by 32 bit signed multiply with 32 bit accumulate, bottom | | 1 | |
| Q setting 16 bit by 32 bit signed multiply with 32 bit accumulate, top | | 1 | |
| Q setting dual 16 bit signed multiply subtract with 32 bit accumulate | | 1 | |
| Q setting dual 16 bit signed multiply subtract with 64 bit accumulate | | 1 | |
| Q setting sum of dual 16 bit signed multiply | | 1 | |
| Unsigned multiply | 32 bit unsigned multiply with double 32 bit accumulation yielding 64 bit result | | 1 |
| Saturate | Q setting dual 16 bit saturate | | 1 |
| Q setting dual 16 bit unsigned saturate | | 1 | |
| Packing and unpacking | Pack halfword top with shifted bottom | | |
| Pack half word bottom with shifted top | | 1 | |
| Extract 8 bits and sign extend to 32 bits | | 1 | |
| Dual extract 8 bits and sign extend each to 16 bits | | 1 | |
| Extract 16 bits and sign extend to 32 bits | | 1 | |
| Extract 8 bits and zero-extend to 32 bits | | 1 | |
| Dual extract 8 bits and zero-extend to 16 bits | | 1 | |
| Extract 16 bits and zero-extend to 32 bits | | 1 | |
| Extract 8 bit to 32 bit unsigned addition | | 1 | |
| Dual extracted 8 bit to 16 bit unsigned addition | | 1 | |
| Extracted 16 bit to 32 bit unsigned addition | | 1 | |
| Extracted 8 bit to 32 bit signed addition | | 1 | |
| Dual extracted 8 bit to 16 bit signed addition | | 1 | |
| Extracted 16 bit to 32 bit signed addition | | 1 | |
| Miscellaneous data processing | Select bytes based on GE bits | | 1 |
| Unsigned sum of quad 8 bit unsigned absolute difference | | 1 | |
| Unsigned sum of quad 8 bit unsigned absolute difference with 32 bit accumulate | | 1 | |
| Addition | Dual 16 bit unsigned saturating addition | | 1 |
| Quad 8 bit unsigned saturating addition | | 1 | |
| Q setting saturating add | | 1 | |
| Q setting dual 16 bit saturating add | | 1 | |
| Q setting quad 8 bit saturating add | | 1 | |
| Q setting saturating double and add | | 1 | |
| GE setting quad 8 bit signed addition | | 1 | |
| GE setting dual 16 bit signed addition | | 1 | |
| Dual 16 bit signed addition with halved results | | 1 | |
| Quad 8 bit signed addition with halved results | | 1 | |
| GE setting dual 16 bit unsigned addition | | 1 | |
| GE setting quad 8 bit unsigned addition | | 1 | |
| Dual 16 bit unsigned addition with halved results | | 1 | |
| Quad 8 bit unsigned addition with halved results | | 1 | |
| Subtraction | Q setting saturating double and subtract | | 1 |
| Dual 16 bit unsigned saturating subtraction | | 1 | |
| Quad 8 bit unsigned saturating subtraction | | 1 | |
| Q setting saturating subtract | | 1 | |
| Q setting dual 16 bit saturating subtract | | 1 | |
| Q setting quad 8 bit saturating subtract | | 1 | |
| Dual 16 bit signed subtraction with halved results | | 1 | |
| Quad 8 bit signed subtraction with halved results | | 1 | |
| GE setting dual 16 bit signed subtraction | | 1 | |
| GE setting quad 8 bit signed subtraction | | 1 | |
| Dual 16 bit unsigned subtraction with halved results | | 1 | |
| Quad 8 bit unsigned subtraction with halved results | | 1 | |
| GE setting dual 16 bit unsigned subtract | | 1 | |
| GE setting quad 8 bit unsigned subtract | | 1 | |
| Parallel addition and subtraction | Dual 16 bit unsigned saturating addition and subtraction with exchange | | 1 |
| Dual 16 bit unsigned saturating subtraction and addition with exchange | | 1 | |
| GE setting dual 16 bit addition and subtraction with exchange | | 1 | |
| Q setting dual 16 bit add and subtract with exchange | | 1 | |
| Q setting dual 16 bit subtract and add with exchange | | 1 | |
| Dual 16 bit signed addition and subtraction with halved results | | 1 | |
| Dual 16 bit signed subtraction and addition with halved results | | 1 | |
| GE setting dual 16 bit signed subtraction and addition with exchange | | 1 | |
| GE setting dual 16 bit unsigned addition and subtraction with exchange | | 1 | |
| Dual 16 bit unsigned addition and subtraction with halved results and exchange | | 1 | |
| Dual 16 bit unsigned subtraction and addition with halved results and exchange | | 1 | |
| GE setting dual 16 bit unsigned subtract and add with exchange | | 1 |