SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
#CPU_ITM_CPU_ITM_MAP1_TABLE_1 lists the memory-mapped registers for the CPU_ITM registers. All register offset addresses not listed in #CPU_ITM_CPU_ITM_MAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
Complex bit access types are encoded to fit into small table cells. #CPU_ITM_CPU_ITM_MAP1_LEGEND shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
STIM0 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM0_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM0_TABLE.
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Stimulus Port 0
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM0 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM0 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA0 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM1 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM1_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM1_TABLE.
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Stimulus Port 1
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM1 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM1 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA1 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM2 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM2_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM2_TABLE.
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Stimulus Port 2
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM2 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM2 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA2 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM3 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM3_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM3_TABLE.
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Stimulus Port 3
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM3 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM3 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA3 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM4 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM4_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM4_TABLE.
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Stimulus Port 4
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM4 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM4 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA4 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM5 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM5_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM5_TABLE.
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Stimulus Port 5
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM5 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM5 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA5 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM6 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM6_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM6_TABLE.
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Stimulus Port 6
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM6 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM6 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA6 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM7 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM7_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM7_TABLE.
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Stimulus Port 7
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM7 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM7 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA7 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM8 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM8_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM8_TABLE.
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Stimulus Port 8
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM8 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM8 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA8 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM9 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM9_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM9_TABLE.
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Stimulus Port 9
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM9 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM9 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA9 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM10 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM10_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM10_TABLE.
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Stimulus Port 10
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM10 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM10 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA10 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM11 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM11_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM11_TABLE.
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Stimulus Port 11
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM11 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM11 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA11 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM12 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM12_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM12_TABLE.
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Stimulus Port 12
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM12 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM12 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA12 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM13 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM13_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM13_TABLE.
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Stimulus Port 13
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM13 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM13 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA13 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM14 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM14_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM14_TABLE.
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Stimulus Port 14
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM14 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM14 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA14 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM15 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM15_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM15_TABLE.
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Stimulus Port 15
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM15 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM15 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA15 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM16 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM16_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM16_TABLE.
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Stimulus Port 16
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM16 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM16 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA16 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM17 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM17_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM17_TABLE.
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Stimulus Port 17
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM17 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM17 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA17 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM18 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM18_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM18_TABLE.
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Stimulus Port 18
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM18 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM18 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA18 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM19 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM19_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM19_TABLE.
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Stimulus Port 19
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM19 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM19 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA19 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM20 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM20_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM20_TABLE.
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Stimulus Port 20
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM20 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM20 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA20 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM21 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM21_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM21_TABLE.
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Stimulus Port 21
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM21 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM21 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA21 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM22 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM22_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM22_TABLE.
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Stimulus Port 22
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM22 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM22 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA22 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM23 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM23_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM23_TABLE.
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Stimulus Port 23
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM23 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM23 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA23 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM24 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM24_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM24_TABLE.
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Stimulus Port 24
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM24 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM24 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA24 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM25 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM25_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM25_TABLE.
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Stimulus Port 25
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM25 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM25 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA25 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM26 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM26_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM26_TABLE.
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Stimulus Port 26
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM26 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM26 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA26 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM27 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM27_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM27_TABLE.
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Stimulus Port 27
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM27 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM27 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA27 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM28 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM28_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM28_TABLE.
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Stimulus Port 28
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM28 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM28 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA28 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM29 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM29_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM29_TABLE.
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Stimulus Port 29
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM29 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM29 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA29 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM30 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM30_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM30_TABLE.
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Stimulus Port 30
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM30 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM30 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA30 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
STIM31 is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM31_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_STIM31_TABLE.
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Stimulus Port 31
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIM31 | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | STIM31 | R/W | X | A write to this location causes data to be written into the FIFO if TER.STIMENA31 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. |
TER is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_TER_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_TER_TABLE.
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Trace Enable
Use the Trace Enable Register to generate trace data by writing to the corresponding stimulus port. Note: Privileged writes are accepted to this register if TCR.ITMENA is set. User writes are accepted to this register if TCR.ITMENA is set and the appropriate privilege mask is cleared. Privileged access to the stimulus ports enables an RTOS kernel to guarantee instrumentation slots or bandwidth as required.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| STIMENA31 | STIMENA30 | STIMENA29 | STIMENA28 | STIMENA27 | STIMENA26 | STIMENA25 | STIMENA24 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| STIMENA23 | STIMENA22 | STIMENA21 | STIMENA20 | STIMENA19 | STIMENA18 | STIMENA17 | STIMENA16 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| STIMENA15 | STIMENA14 | STIMENA13 | STIMENA12 | STIMENA11 | STIMENA10 | STIMENA9 | STIMENA8 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STIMENA7 | STIMENA6 | STIMENA5 | STIMENA4 | STIMENA3 | STIMENA2 | STIMENA1 | STIMENA0 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | STIMENA31 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 31. |
| 30 | STIMENA30 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 30. |
| 29 | STIMENA29 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 29. |
| 28 | STIMENA28 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 28. |
| 27 | STIMENA27 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 27. |
| 26 | STIMENA26 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 26. |
| 25 | STIMENA25 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 25. |
| 24 | STIMENA24 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 24. |
| 23 | STIMENA23 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 23. |
| 22 | STIMENA22 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 22. |
| 21 | STIMENA21 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 21. |
| 20 | STIMENA20 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 20. |
| 19 | STIMENA19 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 19. |
| 18 | STIMENA18 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 18. |
| 17 | STIMENA17 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 17. |
| 16 | STIMENA16 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 16. |
| 15 | STIMENA15 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 15. |
| 14 | STIMENA14 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 14. |
| 13 | STIMENA13 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 13. |
| 12 | STIMENA12 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 12. |
| 11 | STIMENA11 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 11. |
| 10 | STIMENA10 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 10. |
| 9 | STIMENA9 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 9. |
| 8 | STIMENA8 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 8. |
| 7 | STIMENA7 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 7. |
| 6 | STIMENA6 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 6. |
| 5 | STIMENA5 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 5. |
| 4 | STIMENA4 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 4. |
| 3 | STIMENA3 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 3. |
| 2 | STIMENA2 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 2. |
| 1 | STIMENA1 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 1. |
| 0 | STIMENA0 | R/W | 0h | Bit mask to enable tracing on ITM stimulus port 0. |
TPR is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_TPR_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_TPR_TABLE.
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Trace Privilege
This register is used to enable an operating system to control which stimulus ports are accessible by user code. This register can only be used in privileged mode.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-0h | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PRIVMASK | ||||||||||||||
| R/W-0h | R/W-0h | ||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-4 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 3-0 | PRIVMASK | R/W | 0h | Bit mask to enable unprivileged (User) access to ITM stimulus ports: Bit [0] enables stimulus ports 0, 1, ..., and 7. Bit [1] enables stimulus ports 8, 9, ..., and 15. Bit [2] enables stimulus ports 16, 17, ..., and 23. Bit [3] enables stimulus ports 24, 25, ..., and 31. 0: User access allowed to stimulus ports 1: Privileged access only to stimulus ports |
TCR is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_TCR_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_TCR_TABLE.
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Trace Control
Use this register to configure and control ITM transfers. This register can only be written in privilege mode. DWT is not enabled in the ITM block. However, DWT stimulus entry into the FIFO is controlled by DWTENA. If DWT requires timestamping, the TSENA bit must be set.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| BUSY | ATBID | ||||||
| R/W-0h | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | TSPRESCALE | ||||||
| R/W-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SWOENA | DWTENA | SYNCENA | TSENA | ITMENA | ||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 23 | BUSY | R/W | 0h | Set when ITM events present and being drained. |
| 22-16 | ATBID | R/W | 0h | Trace Bus ID for CoreSight system. Optional identifier for multi-source trace stream formatting. If multi-source trace is in use, this field must be written with a non-zero value. |
| 15-10 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 9-8 | TSPRESCALE | R/W | 0h | Timestamp prescaler
0h = No prescaling 1h = Divide by 4 2h = Divide by 16 3h = Divide by 64 |
| 7-5 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 4 | SWOENA | R/W | 0h | Enables asynchronous clocking of the timestamp counter (when TSENA = 1). If TSENA = 0, writing this bit to 1 does not enable asynchronous clocking of the timestamp counter. 0x0: Mode disabled. Timestamp counter uses system clock from the core and counts continuously. 0x1: Timestamp counter uses lineout (data related) clock from TPIU interface. The timestamp counter is held in reset while the output line is idle. |
| 3 | DWTENA | R/W | 0h | Enables the DWT stimulus (hardware event packet emission to the TPIU from the DWT) |
| 2 | SYNCENA | R/W | 0h | Enables synchronization packet transmission for a synchronous TPIU. CPU_DWT:CTRL.SYNCTAP must be configured for the correct synchronization speed. |
| 1 | TSENA | R/W | 0h | Enables differential timestamps. Differential timestamps are emitted when a packet is written to the FIFO with a non-zero timestamp counter, and when the timestamp counter overflows. Timestamps are emitted during idle times after a fixed number of two million cycles. This provides a time reference for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps are triggered by activity on the internal trace bus only. In this case there is no regular timestamp output when the ITM is idle. |
| 0 | ITMENA | R/W | 0h | Enables ITM. This is the master enable, and must be set before ITM Stimulus and Trace Enable registers can be written. |
LAR is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_LAR_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_LAR_TABLE.
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Lock Access
This register is used to prevent write accesses to the Control Registers: TER, TPR and TCR.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LOCK_ACCESS | |||||||||||||||||||||||||||||||
| W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | LOCK_ACCESS | W | 0h | A privileged write of 0xC5ACCE55 enables more write access to Control Registers TER, TPR and TCR. An invalid write removes write access. |
LSR is shown in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_LSR_FIGURE and described in #CPU_ITM_CPU_ITM_MAP1_CPU_ITM_ALL_LSR_TABLE.
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Lock Status
Use this register to enable write accesses to the Control Register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BYTEACC | ACCESS | PRESENT | ||||
| R-0h | R-0h | R-1h | R-1h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-3 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 2 | BYTEACC | R | 0h | Reads 0 which means 8-bit lock access is not be implemented. |
| 1 | ACCESS | R | 1h | Write access to component is blocked. All writes are ignored, reads are permitted. |
| 0 | PRESENT | R | 1h | Indicates that a lock mechanism exists for this component. |