SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
#AON_RTC_AON_RTC_AON_RTC_RMAP_TABLE_1 lists the memory-mapped registers for the AON_RTC registers. All register offset addresses not listed in #AON_RTC_AON_RTC_AON_RTC_RMAP_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
Complex bit access types are encoded to fit into small table cells. #AON_RTC_AON_RTC_AON_RTC_RMAP_LEGEND shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | W 1C |
Write 1 to clear |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
CTL is shown in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_CTL_FIGURE and described in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_CTL_TABLE.
Return to the Summary Table.
Control
This register contains various bitfields for configuration of RTC
RTL Name = CONFIG
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | COMB_EV_MASK | ||||||
| R-0h | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | EV_DELAY | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESET | RESERVED | RTC_4KHZ_EN | RTC_UPD_EN | EN | |||
| W1C-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-19 | RESERVED | R | 0h | Reserved |
| 18-16 | COMB_EV_MASK | R/W | 0h | Eventmask selecting which delayed events that form the
combined event. 0h = No event is selected for combined event. 1h = Use Channel 0 delayed event in combined event 2h = Use Channel 1 delayed event in combined event 4h = Use Channel 2 delayed event in combined event |
| 15-12 | RESERVED | R | 0h | Reserved |
| 11-8 | EV_DELAY | R/W | 0h | Number of SCLK_LF clock cycles waited before
generating delayed events. (Common setting for all RTC cannels) the
delayed event is delayed 0h = No delay on delayed event 1h = Delay by 1 clock cycles 2h = Delay by 2 clock cycles 3h = Delay by 4 clock cycles 4h = Delay by 8 clock cycles 5h = Delay by 16 clock cycles 6h = Delay by 32 clock cycles 7h = Delay by 48 clock cycles 8h = Delay by 64 clock cycles 9h = Delay by 80 clock cycles Ah = Delay by 96 clock cycles Bh = Delay by 112 clock cycles Ch = Delay by 128 clock cycles Dh = Delay by 144 clock cycles |
| 7 | RESET | W1C | 0h | RTC Counter reset. Writing 1 to this bit will reset the RTC counter. This bit is cleared when reset takes effect |
| 6-3 | RESERVED | R | 0h | Reserved |
| 2 | RTC_4KHZ_EN | R/W | 0h | RTC_4KHZ is a 4 KHz reference output, tapped from
SUBSEC.VALUE bit 19 which is used by AUX timer. 0: RTC_4KHZ signal is forced to 0 1: RTC_4KHZ is enabled ( provied that RTC is enabled EN) |
| 1 | RTC_UPD_EN | R/W | 0h | RTC_UPD is a 16 KHz signal used to sync up the radio
timer. The 16 Khz is SCLK_LF divided by 2 0: RTC_UPD signal is forced to 0 1: RTC_UPD signal is toggling @16 kHz |
| 0 | EN | R/W | 0h | Enable RTC counter 0: Halted (frozen) 1: Running |
EVFLAGS is shown in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_EVFLAGS_FIGURE and described in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_EVFLAGS_TABLE.
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Event Flags, RTC Status
This register contains event flags from the 3 RTC
channels. Each flag will be cleared when writing a '1' to the corresponding
bitfield.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | CH2 | ||||||||||||||
| R-0h | R/W1C-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CH1 | RESERVED | CH0 | ||||||||||||
| R-0h | R/W1C-0h | R-0h | R/W1C-0h | ||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R | 0h | Reserved |
| 16 | CH2 | R/W1C | 0h | Channel 2 event flag, set when CHCTL.CH2_EN = 1 and
the RTC value matches or passes the CH2CMP value. An event will be scheduled to occur as soon as possible when writing to CH2CMP provided that the channel is enabled and the new value matches any time between next RTC value and 1 second in the past Writing 1 clears this flag. AUX_SCE can read the flag through AUX_EVCTL:EVSTAT2.AON_RTC_CH2 and clear it using AUX_SYSIF:RTCEVCLR.RTC_CH2_EV_CLR. |
| 15-9 | RESERVED | R | 0h | Reserved |
| 8 | CH1 | R/W1C | 0h | Channel 1 event flag, set when CHCTL.CH1_EN = 1 and
one of the following: - CHCTL.CH1_CAPT_EN = 0 and the RTC value matches or passes the CH1CMP value. - CHCTL.CH1_CAPT_EN = 1 and capture occurs. An event will be scheduled to occur as soon as possible when writing to CH1CMP provided that the channel is enabled, in compare mode and the new value matches any time between next RTC value and 1 second in the past. Writing 1 clears this flag. |
| 7-1 | RESERVED | R | 0h | Reserved |
| 0 | CH0 | R/W1C | 0h | Channel 0 event flag, set when CHCTL.CH0_EN = 1 and
the RTC value matches or passes the CH0CMP value. An event will be scheduled to occur as soon as possible when writing to CH0CMP provided that the channels is enabled and the new value matches any time between next RTC value and 1 second in the past. Writing 1 clears this flag. |
SEC is shown in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_SEC_FIGURE and described in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_SEC_TABLE.
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Second Counter Value, Integer Part
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VALUE | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | VALUE | R/W | 0h | Unsigned integer representing Real Time Clock in
seconds. When reading this register the content of SUBSEC.VALUE is simultaneously latched. A consistent reading of the combined Real Time Clock can be obtained by first reading this register, then reading SUBSEC register. |
SUBSEC is shown in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_SUBSEC_FIGURE and described in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_SUBSEC_TABLE.
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Second Counter Value, Fractional Part
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VALUE | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | VALUE | R/W | 0h | Unsigned integer representing Real Time Clock in
fractions of a second (VALUE/232 seconds) at the time
when SEC register was read. Examples : - 0x0000_0000 = 0.0 sec - 0x4000_0000 = 0.25 sec - 0x8000_0000 = 0.5 sec - 0xC000_0000 = 0.75 sec |
SUBSECINC is shown in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_SUBSECINC_FIGURE and described in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_SUBSECINC_TABLE.
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Subseconds Increment
Value added to SUBSEC.VALUE on every SCLK_LFclock
cycle.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VALUEINC | ||||||||||||||||||||||||||||||
| R-0h | R-00800000h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R | 0h | Reserved |
| 23-0 | VALUEINC | R | 00800000h | This value compensates for a SCLK_LF clock which has
an offset from 32768 Hz. The compensation value can be found as 238 / freq, where freq is SCLK_LF clock frequency in Hertz This value is added to SUBSEC.VALUE on every cycle, and carry of this is added to SEC.VALUE. To perform the addition, bits [23:6] are aligned with SUBSEC.VALUE bits [17:0]. The remaining bits [5:0] are accumulated in a hidden 6-bit register that generates a carry into the above mentioned addition on overflow. The default value corresponds to incrementing by precisely 1/32768 of a second. NOTE: This register is read only. Modification of the register value must be done using registers AUX_SYSIF:RTCSUBSECINC0 , AUX_SYSIF:RTCSUBSECINC1 and AUX_SYSIF:RTCSUBSECINCCTL |
CHCTL is shown in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_CHCTL_FIGURE and described in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_CHCTL_TABLE.
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Channel Configuration
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | CH2_CONT_EN | RESERVED | CH2_EN | ||||
| R-0h | R/W-0h | R-0h | R/W-0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | CH1_CAPT_EN | CH1_EN | |||||
| R-0h | R/W-0h | R/W-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CH0_EN | ||||||
| R-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-19 | RESERVED | R | 0h | Reserved |
| 18 | CH2_CONT_EN | R/W | 0h | Set to enable continuous operation of Channel 2 |
| 17 | RESERVED | R | 0h | Reserved |
| 16 | CH2_EN | R/W | 0h | RTC Channel 2 Enable 0: Disable RTC Channel 2 1: Enable RTC Channel 2 |
| 15-10 | RESERVED | R | 0h | Reserved |
| 9 | CH1_CAPT_EN | R/W | 0h | Set Channel 1 mode 0: Compare mode (default) 1: Capture mode |
| 8 | CH1_EN | R/W | 0h | RTC Channel 1 Enable 0: Disable RTC Channel 1 1: Enable RTC Channel 1 |
| 7-1 | RESERVED | R | 0h | Reserved |
| 0 | CH0_EN | R/W | 0h | RTC Channel 0 Enable 0: Disable RTC Channel 0 1: Enable RTC Channel 0 |
CH0CMP is shown in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_CH0CMP_FIGURE and described in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_CH0CMP_TABLE.
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Channel 0 Compare Value
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VALUE | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | VALUE | R/W | 0h | RTC Channel 0 compare value. Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of the compare value. The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE (31:16) values of the Real Time Clock register. A Cannel 0 event is generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or exciting the compare value. Writing to this register can trigger an immediate*) event in case the new compare value matches a Real Time Clock value from 1 second in the past up till current Real Time Clock value. Example: To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 *) It can take up to one SCLK_LF clock cycles before event occurs due to synchronization. |
CH1CMP is shown in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_CH1CMP_FIGURE and described in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_CH1CMP_TABLE.
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Channel 1 Compare Value
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VALUE | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | VALUE | R/W | 0h | RTC Channel 1 compare value. Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of the compare value. The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE (31:16) values of the Real Time Clock register. A Cannel 0 event is generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or exciting the compare value. Writing to this register can trigger an immediate*) event in case the new compare value matches a Real Time Clock value from 1 second in the past up till current Real Time Clock value. Example: To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 *) It can take up to one SCLK_LF clock cycles before event occurs due to synchronization. |
CH2CMP is shown in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_CH2CMP_FIGURE and described in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_CH2CMP_TABLE.
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Channel 2 Compare Value
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VALUE | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | VALUE | R/W | 0h | RTC Channel 2 compare value. Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of the compare value. The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE (31:16) values of the Real Time Clock register. A Cannel 0 event is generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or exciting the compare value. Writing to this register can trigger an immediate*) event in case the new compare value matches a Real Time Clock value from 1 second in the past up till current Real Time Clock value. Example: To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 *) It can take up to one SCLK_LF clock cycles before event occurs due to synchronization. |
CH2CMPINC is shown in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_CH2CMPINC_FIGURE and described in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_CH2CMPINC_TABLE.
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Channel 2 Compare Value
Auto-increment
This register is primarily used to
generate periodical wake-up for the AUX_SCE module, through the
[AUX_EVCTL.EVSTAT0.AON_RTC] event.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VALUE | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | VALUE | R/W | 0h | If CHCTL.CH2_CONT_EN is set, this value is added to CH2CMP.VALUE on every channel 2 compare event. |
CH1CAPT is shown in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_CH1CAPT_FIGURE and described in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_CH1CAPT_TABLE.
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Channel 1 Capture Value
If CHCTL.CH1_EN = 1and CHCTL.CH1_CAPT_EN = 1, capture
occurs on each rising edge of the event selected in AON_EVENT:RTCSEL.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SEC | SUBSEC | ||||||||||||||||||||||||||||||
| R-0h | R-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | SEC | R | 0h | Value of SEC.VALUE bits 15:0 at capture time. |
| 15-0 | SUBSEC | R | 0h | Value of SUBSEC.VALUE bits 31:16 at capture time. |
SYNC is shown in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_SYNC_FIGURE and described in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_SYNC_TABLE.
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AON Synchronization
This register is used for synchronizing between MCU
and entire AON domain.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | WBUSY | ||||||
| R-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-1 | RESERVED | R | 0h | Reserved |
| 0 | WBUSY | R/W | 0h | This register will always return 0,- however it will
not return the value until there are no outstanding write requests
between MCU and AON Note: Writing to this register prior to reading will force a wait until next SCLK_MF edge. This is recommended for syncing read registers from AON when waking up from sleep Failure to do so may result in reading AON values from prior to going to sleep |
TIME is shown in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_TIME_FIGURE and described in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_TIME_TABLE.
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Current Counter Value
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SEC_L | SUBSEC_H | ||||||||||||||||||||||||||||||
| R-0h | R-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | SEC_L | R | 0h | Returns the lower halfword of SEC register. |
| 15-0 | SUBSEC_H | R | 0h | Returns the upper halfword of SUBSEC register. |
SYNCLF is shown in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_SYNCLF_FIGURE and described in #AON_RTC_AON_RTC_AON_RTC_RMAP_AON_RTC_ALL_SYNCLF_TABLE.
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Synchronization to SCLK_LF
This register is used for synchronizing MCU to
positive or negative edge of SCLK_LF.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHASE | ||||||
| R-0h | R-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-1 | RESERVED | R | 0h | Reserved |
| 0 | PHASE | R | 0h | This bit will always return the SCLK_LF phase. The
return will delayed until a positive or negative edge of SCLK_LF is
seen. 0: Falling edge of SCLK_LF 1: Rising edge of SCLK_LF |