SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
#SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_TABLE_1 lists the memory-mapped registers for the SSI registers. All register offset addresses not listed in #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0h | CR0 | Control 0 | #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_CR0 |
| 4h | CR1 | Control 1 | #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_CR1 |
| 8h | DR | Data | #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_DR |
| Ch | SR | Status | #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_SR |
| 10h | CPSR | Clock Prescale | #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_CPSR |
| 14h | IMSC | Interrupt Mask Set and Clear | #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_IMSC |
| 18h | RIS | Raw Interrupt Status | #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_RIS |
| 1Ch | MIS | Masked Interrupt Status | #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_MIS |
| 20h | ICR | Interrupt Clear | #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_ICR |
| 24h | DMACR | DMA Control | #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_DMACR |
Complex bit access types are encoded to fit into small table cells. #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_LEGEND shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
CR0 is shown in #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_CR0_FIGURE and described in #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_CR0_TABLE.
Return to the Summary Table.
Control 0
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-0h | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SCR | SPH | SPO | FRF | DSS | |||||||||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | RESERVED | R | 0h | Reserved |
| 15-8 | SCR | R/W | 0h | Serial clock rate: This is used to generate the transmit and receive bit rate of the SSI. The bit rate is (SSI's clock frequency)/((SCR+1)*CPSR.CPSDVSR). SCR is a value from 0-255. |
| 7 | SPH | R/W | 0h | CLKOUT phase (Motorola SPI frame format only) This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge. 0h = 1ST_CLK_EDGE : Data is captured on the first clock edge transition. 1h = 2ND_CLK_EDGE : Data is captured on the second clock edge transition. |
| 6 | SPO | R/W | 0h | CLKOUT polarity (Motorola SPI frame format only) 0h = SSI produces
a steady state LOW value on the 1h = SSI produces a steady state HIGH value on the CLKOUT pin when data is not being transferred. |
| 5-4 | FRF | R/W | 0h | Frame format. The supported frame formats are Motorola SPI, TI synchronous serial and National Microwire. Value 0'b11 is reserved and shall not be used. 0h = Motorola SPI frame format 1h = TI synchronous serial frame format 2h = National Microwire frame format |
| 3-0 | DSS | R/W | 0h | Data Size Select. Values 0b0000, 0b0001, 0b0010 are reserved and shall not be used. 3h = 4_BIT : 4-bit data 4h = 5_BIT : 5-bit data 5h = 6_BIT : 6-bit data 6h = 7_BIT : 7-bit data 7h = 8_BIT : 8-bit data 8h = 9_BIT : 9-bit data 9h = 10_BIT : 10-bit data Ah = 11_BIT : 11-bit data Bh = 12_BIT : 12-bit data Ch = 13_BIT : 13-bit data Dh = 14_BIT : 14-bit data Eh = 15_BIT : 15-bit data Fh = 16_BIT : 16-bit data |
CR1 is shown in #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_CR1_FIGURE and described in #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_CR1_TABLE.
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Control 1
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-0h | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SOD | MS | SSE | LBM | |||||||||||
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-4 | RESERVED | R | 0h | Reserved |
| 3 | SOD | R/W | 0h | Slave-mode output disabled This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an SSI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, this bitfield can be set if the SSI slave is not supposed to drive the TXD line: 0: SSI can drive the TXD output in slave mode. 1: SSI cannot drive the TXD output in slave mode. |
| 2 | MS | R/W | 0h | Master or slave mode select. This bit can be modified
only when SSI is disabled, SSE=0. 0h = Device configured as master 1h = Device configured as slave |
| 1 | SSE | R/W | 0h | Synchronous serial interface enable. 0h = SSI_DISABLED : Operation disabled 1h = SSI_ENABLED : Operation enabled |
| 0 | LBM | R/W | 0h | Loop back mode: 0: Normal serial port operation enabled. 1: Output of transmit serial shifter is connected to input of receive serial shifter internally. |
DR is shown in #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_DR_FIGURE and described in #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_DR_TABLE.
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Data
16-bits wide data register:
When read, the entry in
the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data
values are removed by the receive logic from the incoming data frame, they are
placed into the entry in the receive FIFO, pointed to by the current FIFO write
pointer.
When written, the entry in the transmit
FIFO, pointed to by the write pointer, is written to. Data values are removed from
the transmit FIFO one value at a time by the transmit logic. It is loaded into the
transmit serial shifter, then serially shifted out onto the TXD output pin at the
programmed bit rate.
When a data size of less than 16
bits is selected, the user must right-justify data written to the transmit FIFO. The
transmit logic ignores the unused bits. Received data less than 16 bits is
automatically right-justified in the receive buffer.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DATA | ||||||||||||||||||||||||||||||
| R-0h | R/W-X | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | RESERVED | R | 0h | Reserved |
| 15-0 | DATA | R/W | X | Transmit/receive data The values read from this field or written to this field must be right-justified when SSI is programmed for a data size that is less than 16 bits (CR0.DSS != 0b1111). Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. |
SR is shown in #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_SR_FIGURE and described in #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_SR_TABLE.
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Status
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-0h | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BSY | RFF | RNE | TNF | TFE | ||||||||||
| R-0h | R-0h | R-0h | R-0h | R-1h | R-1h | ||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-5 | RESERVED | R | 0h | Reserved |
| 4 | BSY | R | 0h | Serial interface busy: 0: SSI is idle 1: SSI is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. |
| 3 | RFF | R | 0h | Receive FIFO full: 0: Receive FIFO is not full. 1: Receive FIFO is full. |
| 2 | RNE | R | 0h | Receive FIFO not empty 0: Receive FIFO is empty. 1: Receive FIFO is not empty. |
| 1 | TNF | R | 1h | Transmit FIFO not full: 0: Transmit FIFO is full. 1: Transmit FIFO is not full. |
| 0 | TFE | R | 1h | Transmit FIFO empty: 0: Transmit FIFO is not empty. 1: Transmit FIFO is empty. |
CPSR is shown in #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_CPSR_FIGURE and described in #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_CPSR_TABLE.
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Clock Prescale
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CPSDVSR | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R | 0h | Reserved |
| 7-0 | CPSDVSR | R/W | 0h | Clock prescale divisor: This field specifies the division factor by which the input system clock to SSI must be internally divided before further use. The value programmed into this field must be an even non-zero number (2-254). The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. |
IMSC is shown in #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_IMSC_FIGURE and described in #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_IMSC_TABLE.
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Interrupt Mask Set and Clear
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TXIM | RXIM | RTIM | RORIM | |||
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-4 | RESERVED | R | 0h | Reserved |
| 3 | TXIM | R/W | 0h | Transmit FIFO interrupt mask: A read returns the current mask for transmit FIFO interrupt. On a write of 1, the mask for transmit FIFO interrupt is set which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS will not reflect the interrupt. |
| 2 | RXIM | R/W | 0h | Receive FIFO interrupt mask: A read returns the current mask for receive FIFO interrupt. On a write of 1, the mask for receive FIFO interrupt is set which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 clears the mask which means MIS.RXMIS will not reflect the interrupt. |
| 1 | RTIM | R/W | 0h | Receive timeout interrupt mask: A read returns the current mask for receive timeout interrupt. On a write of 1, the mask for receive timeout interrupt is set which means the interrupt state will be reflected in MIS.RTMIS. A write of 0 clears the mask which means MIS.RTMIS will not reflect the interrupt. |
| 0 | RORIM | R/W | 0h | Receive overrun interrupt mask: A read returns the current mask for receive overrun interrupt. On a write of 1, the mask for receive overrun interrupt is set which means the interrupt state will be reflected in MIS.RORMIS. A write of 0 clears the mask which means MIS.RORMIS will not reflect the interrupt. |
RIS is shown in #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_RIS_FIGURE and described in #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_RIS_TABLE.
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Raw Interrupt Status
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TXRIS | RXRIS | RTRIS | RORRIS | |||
| R-0h | R-1h | R-0h | R-0h | R-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-4 | RESERVED | R | 0h | Reserved |
| 3 | TXRIS | R | 1h | Raw transmit FIFO interrupt status: The transmit interrupt is asserted when there are four or fewer valid entries in the transmit FIFO. The transmit interrupt is not qualified with the SSI enable signal. Therefore one of the following ways can be used: - data can be written to the transmit FIFO prior to enabling the SSI and the interrupts. - SSI and interrupts can be enabled so that data can be written to the transmit FIFO by an interrupt service routine. |
| 2 | RXRIS | R | 0h | Raw interrupt state of receive FIFO interrupt: The receive interrupt is asserted when there are four or more valid entries in the receive FIFO. |
| 1 | RTRIS | R | 0h | Raw interrupt state of receive timeout interrupt: The receive timeout interrupt is asserted when the receive FIFO is not empty and SSI has remained idle for a fixed 32 bit period. This mechanism can be used to notify the user that data is still present in the receive FIFO and requires servicing. This interrupt is deasserted if the receive FIFO becomes empty by subsequent reads, or if new data is received on RXD. It can also be cleared by writing to ICR.RTIC. |
| 0 | RORRIS | R | 0h | Raw interrupt state of receive overrun interrupt: The receive overrun interrupt is asserted when the FIFO is already full and an additional data frame is received, causing an overrun of the FIFO. Data is over-written in the receive shift register, but not the FIFO so the FIFO contents stay valid. It can also be cleared by writing to ICR.RORIC. |
MIS is shown in #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_MIS_FIGURE and described in #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_MIS_TABLE.
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Masked Interrupt Status
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TXMIS | RXMIS | RTMIS | RORMIS | |||
| R-0h | R-0h | R-0h | R-0h | R-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-4 | RESERVED | R | 0h | Reserved |
| 3 | TXMIS | R | 0h | Masked interrupt state of transmit FIFO interrupt: This field returns the masked interrupt state of transmit FIFO interrupt which is the AND product of raw interrupt state RIS.TXRIS and the mask setting IMSC.TXIM. |
| 2 | RXMIS | R | 0h | Masked interrupt state of receive FIFO interrupt: This field returns the masked interrupt state of receive FIFO interrupt which is the AND product of raw interrupt state RIS.RXRIS and the mask setting IMSC.RXIM. |
| 1 | RTMIS | R | 0h | Masked interrupt state of receive timeout
interrupt: This field returns the masked interrupt state of receive timeout interrupt which is the AND product of raw interrupt state RIS.RTRIS and the mask setting IMSC.RTIM. |
| 0 | RORMIS | R | 0h | Masked interrupt state of receive overrun
interrupt: This field returns the masked interrupt state of receive overrun interrupt which is the AND product of raw interrupt state RIS.RORRIS and the mask setting IMSC.RORIM. |
ICR is shown in #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_ICR_FIGURE and described in #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_ICR_TABLE.
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Interrupt Clear
On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RTIC | RORIC | |||||
| R-0h | W-0h | W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-2 | RESERVED | R | 0h | Reserved |
| 1 | RTIC | W | 0h | Clear the receive timeout interrupt: Writing 1 to this field clears the timeout interrupt (RIS.RTRIS). Writing 0 has no effect. |
| 0 | RORIC | W | 0h | Clear the receive overrun interrupt: Writing 1 to this field clears the overrun error interrupt (RIS.RORRIS). Writing 0 has no effect. |
DMACR is shown in #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_DMACR_FIGURE and described in #SSP_PL022_R1P4_SSP_PL022_R1P4_MAP1_SSP_PL022_R1P4_ALL_DMACR_TABLE.
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DMA Control
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TXDMAE | RXDMAE | |||||
| R-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-2 | RESERVED | R | 0h | Reserved |
| 1 | TXDMAE | R/W | 0h | Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. |
| 0 | RXDMAE | R/W | 0h | Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. |