SWCU192 User guide | 德州仪器 TI.com.cn

SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

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9. 963
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    1. 968
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  5. 976
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    2. 978
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11. 993
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  3. 996
997

20.3.2.4.3 Instructions

Table 20-4 Memory Word Access

Syntax	Description	Operation	Status Flags				Encoding [15:0]	Prefix
Syntax	Description	Operation	Z	N	C	V	Encoding [15:0]	Prefix
ld Rd, [#addr]	Load direct	Rd = mem[addr]	—	—	—	—	`0ddd.10aa.aaaa.aaaa`	addr
ld Rd, [Rs]	Load indirect	Rd = mem[Rs]	—	—	—	—	`1ddd.1111.0000.1sss`
ld Rd, [Rs++]	Load indirect, post-increment	Rd = mem[Rs], Rs++	—	—	—	—	`1ddd.1111.0001.0sss`
ld Rd, [Rs+R0]	Load indexed	Rd = mem[Rs+R0]	—	—	—	—	`1ddd.1111.0001.1sss`
st Rd, [#addr]	Store direct	mem[addr] = Rd	—	—	—	—	`0ddd.11aa.aaaa.aaaa`	addr
st Rd, [Rs]	Store indirect	mem[Rs] = Rd	—	—	—	—	`1ddd.1111.0010.1sss`
st Rd, [Rs++]	Store indirect, post-increment	mem[Rs] = Rd, Rs++	—	—	—	—	`1ddd.1111.0011.0sss`
st Rd, [Rs+R0]	Store indexed	mem[Rs+R0] = Rd	—	—	—	—	`1ddd.1111.0011.1sss`

Table 20-5 I/O Word Access

Syntax	Description	Operation	Status Flags				Encoding [15:0]	Prefix
Syntax	Description	Operation	Z	N	C	V	Encoding [15:0]	Prefix
in Rd, [#addr]	Input direct	Rd = reg[addr]	—	—	—	—	`1ddd.1001.aaaa.aaaa`	addr
in Rd, [Rs]	Input indirect	Rd = reg[Rs]	—	—	—	—	`1ddd.1111.0000.0sss`
out Rd, [#addr]	Output direct	reg[addr] = Rd	—	—	—	—	`1ddd.1011.aaaa.aaaa`	addr
out Rd, [Rs]	Output indirect	reg[Rs] = Rd	—	—	—	—	`1ddd.1111.0010.0sss`

Table 20-6 I/O Bit Access

Syntax	Description	Operation	Status Flags				Encoding [15:0]	Prefix
Syntax	Description	Operation	Z	N	C	V	Encoding [15:0]	Prefix
iobclr #imm, [#addr]	I/O bit clear direct	reg[addr] &= ~2^imm	—	—	—	—	`010i.01ii.aaaa.aaaa`	addr
iobset #imm, [#addr]	I/O bit set direct	reg[addr] \|= 2^imm	—	—	—	—	`011i.01ii.aaaa.aaaa`	addr
iobtst #imm, [#addr]	I/O bit test direct	reg[addr] & 2^imm	—	—	√	—	`001i.01ii.aaaa.aaaa`	addr

Table 20-7 Register Access

Syntax	Description	Operation	Status Flags				Encoding [15:0]	Prefix
Syntax	Description	Operation	Z	N	C	V	Encoding [15:0]	Prefix
ld Rd, #simm	Load immediate	Rd = simm	—	—	—	—	`0ddd.00ii.iiii.iiii`	simm
ld Rd, Rs	Load register	Rd = Rs	—	—	—	—	`1ddd.1101.0100.0sss`

Table 20-8 Logical Operations

Syntax	Description	Operation	Status Flags				Encoding [15:0]	Prefix
Syntax	Description	Operation	Z	N	C	V	Encoding [15:0]	Prefix
and Rd, #imm	AND immediate	Rd &= imm	x	x	0	0	`1ddd.0000.iiii.iiii`	imm
or Rd, #imm	OR immediate	Rd \|= imm	x	x	0	0	`1ddd.0010.iiii.iiii`	imm
xor Rd, #imm	XOR immediate	Rd ^= imm	x	x	0	0	`1ddd.0100.iiii.iiii`	imm
tst Rd, #imm	Test immediate	Rd & imm	x	x	0	0	`1ddd.1100.iiii.iiii`	imm
and Rd, Rs	AND register	Rd &= Rs	x	x	0	0	`1ddd.1101.0000.0sss`
or Rd, Rs	OR register	Rd \|= Rs	x	x	0	0	`1ddd.1101.0000.1sss`
xor Rd, Rs	XOR register	Rd ^= Rs	x	x	0	0	`1ddd.1101.0001.0sss`
tst Rd, Rs	Test register	Rd & Rs	x	x	0	0	`1ddd.1101.0011.0sss`
inv Rd	Invert register	Rd = ~Rd	x	x	0	0	`1ddd.1101.1001.0010`

Table 20-9 Arithmetic Operations

Syntax	Description	Operation	Status Flags				Encoding [15:0]	Prefix
Syntax	Description	Operation	Z	N	C	V	Encoding [15:0]	Prefix
add Rd, #simm	Add immediate	Rd += simm	x	x	x	x	`1ddd.1000.iiii.iiii`	simm
cmp Rd, #simm	Compare immediate	Rd – simm	x	x	x	x	`1ddd.1010.iiii.iiii`	simm
sub Rd, Rs	Subtract register	Rd -= Rs	x	x	x	x	`1ddd.1101.0001.1sss`
add Rd, Rs	Add register	Rd += Rs	x	x	x	x	`1ddd.1101.0010.0sss`
cmp Rd, Rs	Compare register	Rd – Rs	x	x	x	x	`1ddd.1101.0010.1sss`
subr Rd, Rs	Subtract reverse register	Rd = Rs – Rd	x	x	x	x	`1ddd.1101.0011.1sss`
abs Rd	Absolute register	Rd = (Rd >= 0) ? Rd : -Rd	x	x	x	x	`1ddd.1101.1001.0000`
neg Rd	Negate register	Rd = -Rd	x	x	x	x	`1ddd.1101.1001.0001`

Table 20-10 Shift Operations

Syntax	Description	Operation	Status Flags				Encoding [15:0]	Prefix
Syntax	Description	Operation	Z	N	C	V	Encoding [15:0]	Prefix
lsl Rd, Rs	Logical shift left register	Rd <<= Rs	x	x	x	0	`1ddd.1101.1000.0sss`
lsr Rd, Rs	Logical shift right register	Rd >>= Rs	x	x	x	0	`1ddd.1101.1000.1sss`
asr Rd, Rs	Arithmetic shift right register	Rd >>= Rs, preserve sign	x	x	x	0	`1ddd.1101.1001.1sss`
lsl Rd, #imm	Logical shift left immediate⁽¹⁾	Rd <<= imm	x	x	x	0	`1ddd.1101.1010.0iii`
lsr Rd, #imm	Logical shift right immediate⁽¹⁾	Rd >>= imm	x	x	x	0	`1ddd.1101.1010.1iii`
asr Rd, #imm	Arithmetic shift right immediate⁽¹⁾	Rd >>= imm, preserve sign	x	x	x	0	`1ddd.1101.1011.1iii`

(1) Shift immediate can be 1 to 8 bits, where imm = 0 corresponds to 8 bits.

Table 20-11 Program Flow Control

Syntax	Description	Operation	Status Flags				Encoding [15:0]	Prefix
Syntax	Description	Operation	Z	N	C	V	Encoding [15:0]	Prefix
jmp addr	Jump direct	pc = addr	—	—	—	—	`0000.01aa.aaaa.aaaa`	addr
jsr addr	Jump subroutine direct	push(stack, pc + 1), pc = addr	—	—	—	—	`0001.01aa.aaaa.aaaa`	addr
jmp R0	Jump indirect	pc = R0	—	—	—	—	`1000.1101.1011.0111`
jsr R0	Jump subroutine indirect	push(stack, pc + 1), pc = R0	—	—	—	—	`1001.1101.1011.0111`
rts	Return subroutine	pc = pop(stack)	—	—	—	—	`1010.1101.1011.0111`
bra rel	Branch relative	pc = pc + 1 + rel	—	—	—	—	`1000.1110.rrrr.rrrr`
b<cc> rel	Branch relative if condition is met	if (cc) pc = pc + 1 + rel	—	—	—	—	`1ccc.c110.rrrr.rrrr`
bev0 #ev, rel	Branch if event 0	if (!events[ev]) pc = pc + 1 + rel	—	—	—	—	`1eee.0001.rrrr.rrrr`
bev01#ev, rel	Branch if event 1	if (events[ev]) pc = pc + 1 + rel	—	—	—	—	`1eee.0011.rrrr.rrrr`

For all other instructions and also when not taking a conditional branch, the program counter is incremented by 1: pc = pc + 1. See Table 20-12 for the conditional operations.

Table 20-12 Program Flow Conditions

Syntax <cc>	Description	Condition	Encoding [3:0]
gtu	Greater than, unsigned	!C & !Z	`0010`
geu / iob0	Greater than or equal to, unsigned / Tested I/O bit = 0	!C	`0100`
eq / z	Equal / Zero	Z	`0110`
novf	Not overflow	!V	`1000`
pos	Positive	!N	`1010`
ges	Greater or equal to, signed	(N & V) \| (!N & !V)	`1100`
gts	Greater than, signed	((N & V) \| (!N & !V)) & !Z	`1110`
leu	Less than or equal to, unsigned	C \| Z	`0011`
ltu / iob1	Less than, unsigned / Tested I/O bit = 1	C	`0101`
neq / nz	Not equal / Non-zero	!Z	`0111`
ovf	Overflow	V	`1001`
neg	Negative	N	`1011`
lts	Less than, signed	(N & !V) \| (!N & V)	`1101`
les	Less than or equal to, signed	(N & !V) \| (!N & V) \| Z	`1111`

Table 20-13 Loop Flow Control

Syntax	Description	Operation	Status Flags				Encoding [15:0]	Prefix
Syntax	Description	Operation	Z	N	C	V	Encoding [15:0]	Prefix
loop R1, rel	Loop register, n = 1..255⁽¹⁾	lc = LSB(R1), ls = pc + 1, le = pc + rel	x	x	x	x	`1000.0101.rrrr.rrrr`
loop #n, rel	Loop immediate, n = 2^x (x = 1..7)⁽¹⁾	lc = n, ls = pc + 1, le = pc + rel	x	x	x	x	`1nnn.0101.rrrr.rrrr`

(1) The assembler offsets the end-of-loop label so it can be placed after the last instruction of the loop.

Table 20-14 Power Management

Syntax	Description	Operation	Status Flags				Encoding [15:0]	Prefix
Syntax	Description	Operation	Z	N	C	V	Encoding [15:0]	Prefix
wev0 #ev	Wait for event 0	Stop until events[ev] == 0	x	x	x	x	`1eee.1101.1011.0000`
wev1 #ev	Wait for event 1	Stop until events[ev] == 1	x	x	x	x	`1eee.1101.1011.0001`
sleep	Sleep	Stop until wakeup, then pc = 2 * vector	x	x	x	x	`1011.1101.1011.0111`

Table 20-15 Miscellaneous

Syntax	Description	Operation	Status Flags				Encoding [15:0]	Prefix
Syntax	Description	Operation	Z	N	C	V	Encoding [15:0]	Prefix
nop	No operation	R7 = R7 (no effect)	x	x	x	x	`1111.1101.0100.0111`
pfix #imm	Prefix⁽¹⁾	Use prefix on next instruction	x	x	x	x	`1000.0110.iiii.iiii`
dw #imm	Data word	Inserts 16-bit immediate data value	x	x	x	x	`iiii.iiii.iiii.iiii`

(1) The prefix (


pfix

) instruction is inserted automatically by the assembler where needed. Do not insert this instruction manually.