SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
23.4.4.3 Motorola SPI Frame Format With SPO = 0 and SPH = 0
Figure 23-4 and Figure 23-5 show single and continuous transmission signal sequences for Motorola SPI format with SPO = 0 and SPH = 0, respectively.
Figure 23-5 Motorola SPI Format (Continuous Transfer) With SPO = 0 and SPH = 0
In this configuration, the following occurs during idle periods:
- SSIn_CLK is forced low
- SSIn_FSS is forced high
- The transmit data line SSIn_TX is arbitrarily forced low
- When the SSI is configured as a master, the SSI enables the SSIn_CLK DIO
- When the SSI is configured as a slave, the SSI disables the SSIn_CLK DIO
If the SSI is enabled and valid data is in the TX FIFO, the SSIn_FSS master signal is driven low at the start of transmission which causes enabling of slave data onto the SSIn_RX input line of the master. The master SSIn_TX output DIO is enabled.
One-half SSIn_CLK period later, valid master data is transferred to the SSIn_TX pin. Once both the master and slave data are set, the SSIn_CLK master clock pin goes high after an additional one-half SSIn_CLK period.
The data is now captured on the rising edges and propagated on the falling edges of the SSIn_CLK signal.
For a single-word transmission after all bits of the data word are transferred, the SSIn_FSS line is returned to its IDLE high state one SSIn_CLK period after the last bit is captured.
For continuous back-to-back transmissions, the SSIn_FSS signal must pulse high between each data word transfer because the slave-select pin freezes the data in its serial peripheral register and does not allow altering of the data if the SPH bit is clear. The master device must raise the SSIn_FSS pin of the slave device between each data transfer to enable the serial peripheral data write. When the continuous transfer completes, the SSIn_FSS pin is returned to its IDLE state one SSIn_CLK period after the last bit is captured.