SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The Arm® Cortex®-M4F processor and the nested vectored interrupt controller (NVIC) prioritize and handle all exceptions in handler mode. The state of the processor is automatically stored to the stack on an exception and automatically restored from the stack at the end of the interrupt service routine (ISR). The vector is fetched in parallel to state saving, thus enabling efficient interrupt entry. The processor supports tail-chaining, which enables performance of back-to-back interrupts without the overhead of state saving and restoration.
Table 6-1 lists all exception types. Software can set eight priority levels on seven of these exceptions (system handlers) as well as on the interrupts of the CC13x2x7 and CC26x2x7 device platform (listed in Table 6-7).
Priorities on the system handlers are set with the NVIC System Handler Priority n registers (CPU_SCS:SHPRn in Section 3.9.4). Interrupts are enabled through the NVIC Interrupt Set Enable n register (CPU_SCS:NVIC_ISERn in Section 3.9.4) and prioritized with the NVIC Interrupt Priority n registers (CPU_SCS:NVIC_IPRn in Section 3.9.4). Priorities can be grouped by splitting priority levels into preemption priorities and subpriorities. All the interrupt registers are described in Section 5.2.2.
Internally, the highest user-programmable priority (0) is treated as third priority, after a reset, and a hard fault, in that order.
The default priority is 0 for all the programmable priorities.
After a write to clear an interrupt source, it may take several processor cycles for the NVIC to detect the interrupt source deassertion due to the write buffer. Thus, if the interrupt clear is done as the last action in an interrupt handler, it is possible for the interrupt handler to complete while the NVIC detects the interrupt as still asserted, causing the interrupt handler to be re-entered errantly. This situation can be avoided by either clearing the interrupt source at the beginning of the interrupt handler or by performing a read from the same address after the write to clear the interrupt source (and flush the write buffer).
For more information on exceptions and interrupts, see Section 5.2.2.