SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The following software example in pseudocode describes the actions that are typically executed by the host software to authenticate a message, stored in external memory, with AES-CBC-MAC mode. The result TAG is read using the slave interface.
The following sequence processes a packet of at least 1 input data byte.
// configure the master control module
write ALGSEL 0x0000_0002 // enable the DMA path to the AES engine
write IRQCLR 0x0000_0001 // clear any outstanding events
// configure the key store to provide a pre-loaded AES key
write KEYREADAREA 0x0000_0000 // load the key from ram area 0 (NOTE: The key
// must be pre-loaded to this area)
wait KEYREADAREA[31]==’0’ // wait until the key is loaded to the AES module
check IRQSTAT[29] = ‘0’// check that the key is loaded without errors
// write the initialization vector
write AESIV_0
...
write AESIV_3
// configure the AES engine
write AESCTL = 0b0010_0000_0000_0000_
1000_0000_0100_1100 // program AES-CBC-MAC-128 authentication
write AESDATALEN0 // write length of the crypto block (lo)
write AESDATALEN1 // write the length of the crypto block (hi)
// (may be non-block size aligned)
/write DMACH0CTL 0x0000_00001 // enable DMA channel 0/ configure DMAC
write DMACH0EXTADDR <address> // base address of the input data in ext. memory
write DMACH0LEN <length> // input data length in bytes, equal to the message
// length len({aad data, pad, crypto_data, pad})
// (may be non-block size aligned)
// wait for completion
wait IRQSTAT[0]==’1’ // wait for operation completed
check IRQSTAT[31]==‘0’ // check for the absence of errors
write ALGSEL 0x0000_0000 // disable master control/DMA clock
// read tag
wait AESCTL[30]==’1’ // wait for the SAVED_CONTEXT_RDY bit [30]
read AESTAGOUT__0 - AESTAGOUT__3 // this read clears the SAVED_CONTEXT_RDY flag
// end of algorithm