SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The bootloader supports updating through the UART0 and SSI0 ports, which are available on the CC13x2x7 and CC26x2x7 device platform. The SSI0 port has the advantage of supporting higher and more flexible data rates, but it also requires more connections to the CC13x2x7 and CC26x2x7 device platform. The UART0 has the disadvantage of having slightly lower and possibly less flexible rates. However, the UART0 requires fewer pins and can be easily implemented with any standard UART connection.
Table 11-2 specifies which serial interface signals are configured to specific DIOs. These pins are fixed and cannot be reconfigured.
| Signal | CC26x2R | CC1312R | CC1352x |
|---|---|---|---|
| UART0_RX | DIO2 | DIO2 | DIO12 |
| UART0_TX | DIO3 | DIO3 | DIO13 |
| SSI0_CLK | DIO10 | DIO10 | DIO10 |
| SSI0_FSS | DIO11 | DIO11 | DIO11 |
| SSI0_RX | DIO9 | DIO9 | DIO9 |
| SSI0_TX | DIO8 | DIO8 | DIO8 |
The bootloader initially configures only the input pins on the two serial interfaces. By default, all I/O pins have their input buffers disabled, so the bootloader configures the required pins to be input pins so that the bootloader interface is not accessible from a host before this point in time. For this initial configuration of input pins, the firmware configures the IOC to route the input signals listed in Table 11-2 to their corresponding peripheral signals.
The bootloader selects the interface that is the first to be accessed by the external device. Once selected, the TX output pin for the selected interface is configured; the module on the inactive interface (UART0 or SSI0) is disabled. To switch to the other interface, the CC13x2x7 and CC26x2x7 device platform must be reset. The delayed configuration of the TX pin imposes special consideration on an SSI0 master device regarding the transfer of the first byte of the first packet (see Section 11.2.2.2).