SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
7.3.3 Router Scan Chain
This register accesses all TAP linking and control registers. The scan chain is 32 bits long. For more information, see Figure 7-11 and Table 7-12.
Figure 7-11 ROUTER DR Scan Chain| Bit | Field | Width | Type | Reset | Description |
|---|---|---|---|---|---|
| 31 | Write Enable | 1 | W | 0 | On scan-in: 0: Only a read is performed. 1: A write to the specified register is performed. On scan-out: If the previous scan resulted in a write to a ROUTER addressed register, then when bit 31 is scanned out during the next trip through the Shift DR state, it indicates whether the previous write succeeded. If 1, the previous write failed. If 0, the previous write was successful. A write to a debug or test secondary TAP control and status register may fail for a number of reasons including:
|
| 30–28 | Block Select | 3 | R/W | 000 | Block select: |
| 27–24 | Register Number | 4 | R/W | 0000 | This field specifies the register within the selected block (see Table 7-13, Table 7-15, and Table 7-20). |
| 23–0 | Selected Register Contents | 24 | – | – | Based on the values in Block Select and Register Number fields; the corresponding register is mapped to this field. |
During the Capture DR state, the Data Shift register is inspected. The register specified by the Block and Register fields is read and the value is placed in the lower 24 bits of the Data Shift register.
The current contents of the Data Shift register were those loaded by the previous scan.
The register specified in DR scan n 1 is read during scan n. Of course, if an intervening IR scan occurs, the contents of the Data Shift register are unpredictable, so a read of the register indicated in DR scan n 1 does not occur.
Sometimes an action on the destination register is still pending when the Update DR state is reached. Some of the bits of the destination register may not be changed while the action is pending, such as the reset controls signals have been written but not acted upon yet. Therefore, the new value indicated by this write may not be applied to the register. If this happens, the write to the ICEPick register is suppressed and the write-failure flag is set to 1. The write-failure bit is captured into the Data Shift register at bit 31. When the value is captured, the WF flag is cleared.
If bit 31 indicates that a read must be performed, the ICEPick register specified is not touched at this point. The ICEPick register contents remain undisturbed.
If the contents of the Data Shift register remain constant until the next Capture DR state, then the specified register is read at that point. An intervening IR scan disturbs the Data Shift register contents and as a consequence, it cannot be assured that the register specified will be read.
There is no address buffering within the ICEPick for the read block and register other than the Data Shift register. No extra storage is needed when the proper scan sequence is followed. For the sequence, see Section 7.5.