SWCU192 User guide | 德州仪器 TI.com.cn

SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

1
1. 2
2. 3
3. 4
4. 5
5. 6
7
1. 8
2. 9
3. 10
  1. 11
    1. 12
    2. 13
    3. 14
    4. 15
  2. 16
    1. 17
    2. 18
    3. 19
  3. 20
  4. 21
  5. 22
    1. 23
    2. 24
  6. 25
  7. 26
  8. 27
    1. 28
    2. 29
    3. 30
    4. 31
  9. 32
  10. 33
  11. 34
  12. 35
  13. 36
    1. 37
      1. 38
      2. 39
      3. 40
      4. 41
    2. 42
43
1. 44
2. 45
3. 46
  1. 47
  2. 48
  3. 49
  4. 50
  5. 51
  6. 52
4. 53
  1. 54
  2. 55
  3. 56
  4. 57
5. 58
  1. 59
  2. 60
    1. 61
    2. 62
    3. 63
    4. 64
    5. 65
    6. 66
    7. 67
    8. 68
    9. 69
    10. 70
    11. 71
    12. 72
    13. 73
    14. 74
    15. 75
    16. 76
    17. 77
    18. 78
    19. 79
    20. 80
    21. 81
6. 82
  1. 83
  2. 84
  3. 85
7. 86
  1. 87
  2. 88
    1. 89
    2. 90
      1. 91
      2. 92
      3. 93
    3. 94
    4. 95
    5. 96
    6. 97
      1. 98
      2. 99
      3. 100
    7. 101
  3. 102
    1. 103
      1. 104
8. 105
  1. 106
  2. 107
  3. 108
9. 109
  1. 110
  2. 111
  3. 112
  4. 113
  5. 114
115
1. 116
117
1. 118
2. 119
  1. 120
  2. 121
    1. 122
    2. 123
  3. 124
  4. 125
  5. 126
  6. 127
  7. 128
129
1. 130
  1. 131
  2. 132
  3. 133
  4. 134
  5. 135
  6. 136
  7. 137
    1. 138
    2. 139
2. 140
  1. 141
  2. 142
  3. 143
  4. 144
3. 145
  1. 146
  2. 147
    1. 148
4. 149
  1. 150
  2. 151
    1. 152
    2. 153
    3. 154
5. 155
  1. 156
  2. 157
    1. 158
    2. 159
    3. 160
6. 161
7. 162
  1. 163
  2. 164
165
1. 166
2. 167
  1. 168
    1. 169
  2. 170
    1. 171
    2. 172
    3. 173
3. 174
  1. 175
    1. 176
    2. 177
  2. 178
    1. 179
    2. 180
    3. 181
    4. 182
    5. 183
    6. 184
    7. 185
    8. 186
  3. 187
  4. 188
    1. 189
      1. 190
      2. 191
      3. 192
    2. 193
      1. 194
    3. 195
      1. 196
4. 197
5. 198
6. 199
7. 200
8. 201
9. 202
10. 203
204
1. 205
2. 206
3. 207
  1. 208
4. 209
  1. 210
    1. 211
  2. 212
    1. 213
5. 214
  1. 215
    1. 216
  2. 217
    1. 218
    2. 219
    3. 220
  3. 221
6. 222
  1. 223
  2. 224
  3. 225
  4. 226
  5. 227
7. 228
  1. 229
    1. 230
    2. 231
    3. 232
  2. 233
  3. 234
8. 235
  1. 236
  2. 237
  3. 238
239
1. 240
2. 241
  1. 242
    1. 243
    2. 244
    3. 245
  2. 246
  3. 247
  4. 248
3. 249
  1. 250
  2. 251
    1. 252
    2. 253
    3. 254
4. 255
5. 256
  1. 257
  2. 258
  3. 259
  4. 260
6. 261
7. 262
  1. 263
  2. 264
265
1. 266
2. 267
3. 268
4. 269
5. 270
6. 271
7. 272
  1. 273
  2. 274
275
1. 276
  1. 277
  2. 278
2. 279
  1. 280
    1. 281
  2. 282
    1. 283
      1. 284
    2. 285
  3. 286
    1. 287
    2. 288
    3. 289
    4. 290
    5. 291
    6. 292
    7. 293
    8. 294
    9. 295
    10. 296
    11. 297
    12. 298
    13. 299
300
1. 301
2. 302
  1. 303
3. 304
4. 305
  1. 306
307
1. 308
2. 309
  1. 310
  2. 311
3. 312
4. 313
  1. 314
  2. 315
  3. 316
5. 317
  1. 318
  2. 319
  3. 320
    1. 321
    2. 322
  4. 323
    1. 324
      1. 325
    2. 326
      1. 327
    3. 328
  5. 329
    1. 330
    2. 331
    3. 332
    4. 333
    5. 334
  6. 335
    1. 336
    2. 337
    3. 338
    4. 339
    5. 340
6. 341
  1. 342
  2. 343
7. 344
  1. 345
  2. 346
    1. 347
    2. 348
    3. 349
  3. 350
    1. 351
    2. 352
      1. 353
      2. 354
      3. 355
    3. 356
      1. 357
    4. 358
      1. 359
      2. 360
  4. 361
    1. 362
    2. 363
      1. 364
    3. 365
      1. 366
      2. 367
      3. 368
      4. 369
    4. 370
      1. 371
    5. 372
      1. 373
    6. 374
      1. 375
  5. 376
    1. 377
    2. 378
    3. 379
      1. 380
      2. 381
        
        382
      3.        383
        
                384
        
                385
        
                 386
        
                 387
        
                 388
        
                 389
        
                 390
        
                 391
        
                 392
        
                 393
        
                394
        
                395
        
                396
8. 397
  1. 398
    1. 399
    2. 400
  2. 401
9. 402
  1. 403
404
1. 405
2. 406
3. 407
  1. 408
  2. 409
  3. 410
  4. 411
4. 412
  1. 413
5. 414
6. 415
7. 416
8. 417
9. 418
  1. 419
    1. 420
    2. 421
10. 422
  1. 423
  2. 424
  3. 425
426
1. 427
2. 428
3. 429
  1. 430
  2. 431
  3. 432
  4. 433
    1. 434
    2. 435
  5. 436
  6. 437
    1. 438
    2. 439
    3. 440
    4. 441
    5. 442
    6. 443
  7. 444
  8. 445
  9. 446
  10. 447
4. 448
  1. 449
  2. 450
    1. 451
    2. 452
    3. 453
5. 454
  1. 455
456
1. 457
2. 458
3. 459
  1. 460
  2. 461
    1. 462
    2. 463
    3. 464
    4. 465
    5. 466
  3. 467
  4. 468
4. 469
  1. 470
  2. 471
  3. 472
  4. 473
  5. 474
5. 475
  1. 476
477
1. 478
2. 479
  1. 480
  2. 481
  3. 482
    1. 483
  4. 484
3. 485
  1. 486
  2. 487
  3. 488
4. 489
  1. 490
491
1. 492
2. 493
3. 494
4. 495
  1. 496
497
1. 498
2. 499
3. 500
4. 501
5. 502
  1. 503
  2. 504
  3. 505
6. 506
  1. 507
    1. 508
    2. 509
    3. 510
      1. 511
      2. 512
7. 513
  1. 514
515
1. 516
  1. 517
2. 518
  1. 519
    1. 520
  2. 521
    1. 522
    2. 523
  3. 524
  4. 525
3. 526
  1. 527
    1. 528
    2. 529
    3. 530
    4. 531
  2. 532
    1. 533
      1. 534
    2. 535
      1. 536
      2. 537
    3. 538
      1. 539
    4. 540
      1. 541
      2. 542
      3. 543
    5. 544
    6. 545
    7. 546
    8. 547
    9. 548
    10. 549
4. 550
  1. 551
    1. 552
  2. 553
    1. 554
    2. 555
      1. 556
      2. 557
      3. 558
      4. 559
      5. 560
  3. 561
    1. 562
    2. 563
    3. 564
  4. 565
    1. 566
    2. 567
      1. 568
      2. 569
      3. 570
  5. 571
    1. 572
    2. 573
      1. 574
      2. 575
      3. 576
      4.        577
        
                578
        
                579
      5. 580
      6. 581
    3. 582
      1. 583
      2. 584
      3.        585
        
                586
        
                587
        
                588
        
                589
      4. 590
  6. 591
    1. 592
    2. 593
  7. 594
    1. 595
    2. 596
      1. 597
      2. 598
      3. 599
      4. 600
      5.        601
        
                602
        
                 603
        
                604
        
                 605
        
                606
        
                 607
      6. 608
5. 609
  1. 610
    1. 611
    2. 612
  2. 613
    1. 614
    2. 615
      1. 616
      2. 617
      3. 618
      4. 619
      5. 620
      6. 621
      7. 622
      8. 623
  3. 624
    1. 625
    2. 626
      1. 627
      2. 628
      3. 629
      4. 630
  4. 631
    1. 632
    2. 633
      1. 634
      2. 635
      3.        636
        
                637
        
                638
  5. 639
    1. 640
    2. 641
      1. 642
      2. 643
      3.        644
        
                645
        
                646
        
                647
      4.        648
        
                649
        
                650
        
                651
        
                652
      5. 653
      6. 654
  6. 655
    1. 656
    2. 657
      1. 658
      2. 659
      3. 660
      4. 661
      5. 662
6. 663
  1. 664
    1. 665
    2. 666
      1.        667
        
                668
        
                669
  2. 670
  3. 671
  4. 672
  5. 673
  6. 674
  7. 675
7. 676
8. 677
  1. 678
  2. 679
  3. 680
  4. 681
  5. 682
  6. 683
  7. 684
  8. 685
  9. 686
  10. 687
  11. 688
  12. 689
690
1. 691
2. 692
3. 693
  1. 694
695
1. 696
2. 697
3. 698
4. 699
  1. 700
  2. 701
  3. 702
  4. 703
    1. 704
    2. 705
      1. 706
      2. 707
  5. 708
  6. 709
  7. 710
5. 711
6. 712
7. 713
  1. 714
715
1. 716
2. 717
3. 718
4. 719
  1. 720
  2. 721
    1. 722
    2. 723
  3. 724
  4. 725
    1. 726
    2. 727
      1. 728
      2. 729
    3. 730
    4. 731
    5. 732
    6. 733
    7. 734
5. 735
6. 736
7. 737
  1. 738
739
1. 740
2. 741
3. 742
  1. 743
    1. 744
    2. 745
    3. 746
    4. 747
    5. 748
  2. 749
    1. 750
  3. 751
    1. 752
    2. 753
  4. 754
  5. 755
    1. 756
    2. 757
4. 758
5. 759
  1. 760
761
1. 762
2. 763
3. 764
4. 765
  1. 766
    1. 767
  2. 768
  3. 769
  4. 770
    1. 771
  5. 772
    1. 773
  6. 774
    1. 775
  7. 776
    1. 777
  8. 778
    1. 779
    2. 780
5. 781
  1. 782
  2. 783
  3. 784
  4. 785
    1. 786
    2. 787
    3. 788
6. 789
  1. 790
  2. 791
  3. 792
  4. 793
7. 794
8. 795
  1. 796
  2. 797
9. 798
  1. 799
800
1. 801
  1. 802
2. 803
  1. 804
  2. 805
  3. 806
    1. 807
    2. 808
    3. 809
  4. 810
    1. 811
    2. 812
    3. 813
3. 814
  1. 815
  2. 816
    1. 817
    2. 818
    3. 819
    4. 820
    5. 821
      1. 822
      2. 823
      3. 824
    6. 825
      1. 826
    7. 827
      1. 828
      2. 829
      3. 830
      4. 831
    8. 832
  3. 833
    1. 834
      1. 835
      2. 836
      3. 837
      4. 838
      5. 839
      6. 840
      7. 841
      8. 842
      9. 843
      10. 844
      11. 845
      12. 846
      13. 847
      14. 848
    2. 849
      1. 850
      2. 851
      3. 852
      4. 853
      5. 854
      6. 855
      7. 856
      8. 857
      9. 858
      10. 859
      11. 860
      12. 861
      13. 862
      14. 863
      15. 864
      16. 865
      17. 866
      18. 867
      19. 868
      20. 869
  4. 870
    1. 871
    2. 872
    3. 873
    4. 874
    5. 875
4. 876
  1. 877
    1. 878
    2. 879
    3. 880
    4. 881
    5. 882
  2. 883
    1. 884
    2. 885
5. 886
  1. 887
    1. 888
    2. 889
    3. 890
    4. 891
  2. 892
  3. 893
    1. 894
    2. 895
  4. 896
    1. 897
      1.        898
        
                899
        
                900
      2. 901
      3. 902
      4. 903
      5. 904
    2. 905
    3. 906
    4. 907
    5. 908
    6. 909
  5. 910
    1. 911
    2. 912
    3. 913
    4. 914
    5. 915
    6. 916
6. 917
  1. 918
    1. 919
      1. 920
    2. 921
    3. 922
    4. 923
  2. 924
7. 925
  1. 926
  2. 927
8. 928
  1. 929
  2. 930
  3. 931
  4. 932
  5. 933
  6. 934
  7. 935
  8. 936
    1. 937
    2. 938
    3. 939
    4. 940
  9. 941
    1. 942
    2. 943
    3. 944
  10. 945
    1. 946
    2. 947
    3. 948
    4. 949
    5. 950
  11. 951
    1. 952
    2. 953
    3. 954
    4. 955
    5. 956
  12. 957
  13. 958
  14. 959
  15. 960
  16. 961
  17. 962
9. 963
  1. 964
10. 965
  1. 966
  2. 967
    1. 968
      1. 969
    2. 970
    3. 971
  3. 972
  4. 973
    1. 974
    2. 975
  5. 976
    1. 977
    2. 978
      1. 979
    3. 980
      1. 981
      2. 982
    4. 983
      1. 984
      2. 985
    5. 986
      1. 987
      2. 988
      3. 989
  6. 990
    1. 991
    2. 992
11. 993
  1. 994
  2. 995
  3. 996
997

14.10.3 MCU_IOC Registers

#MCU_IOC_MCU_IOC_MAP1_TABLE_1 lists the memory-mapped registers for the MCU_IOC registers. All register offset addresses not listed in #MCU_IOC_MCU_IOC_MAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 14-28 MCU_IOC Registers

Offset	Acronym	Register Name	Section
0h	IOCFG0	Configuration of DIO0	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG0
4h	IOCFG1	Configuration of DIO1	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG1
8h	IOCFG2	Configuration of DIO2	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG2
Ch	IOCFG3	Configuration of DIO3	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG3
10h	IOCFG4	Configuration of DIO4	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG4
14h	IOCFG5	Configuration of DIO5	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG5
18h	IOCFG6	Configuration of DIO6	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG6
1Ch	IOCFG7	Configuration of DIO7	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG7
20h	IOCFG8	Configuration of DIO8	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG8
24h	IOCFG9	Configuration of DIO9	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG9
28h	IOCFG10	Configuration of DIO10	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG10
2Ch	IOCFG11	Configuration of DIO11	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG11
30h	IOCFG12	Configuration of DIO12	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG12
34h	IOCFG13	Configuration of DIO13	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG13
38h	IOCFG14	Configuration of DIO14	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG14
3Ch	IOCFG15	Configuration of DIO15	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG15
40h	IOCFG16	Configuration of DIO16	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG16
44h	IOCFG17	Configuration of DIO17	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG17
48h	IOCFG18	Configuration of DIO18	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG18
4Ch	IOCFG19	Configuration of DIO19	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG19
50h	IOCFG20	Configuration of DIO20	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG20
54h	IOCFG21	Configuration of DIO21	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG21
58h	IOCFG22	Configuration of DIO22	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG22
5Ch	IOCFG23	Configuration of DIO23	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG23
60h	IOCFG24	Configuration of DIO24	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG24
64h	IOCFG25	Configuration of DIO25	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG25
68h	IOCFG26	Configuration of DIO26	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG26
6Ch	IOCFG27	Configuration of DIO27	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG27
70h	IOCFG28	Configuration of DIO28	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG28
74h	IOCFG29	Configuration of DIO29	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG29
78h	IOCFG30	Configuration of DIO30	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG30
7Ch	IOCFG31	Configuration of DIO31	#MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG31

Complex bit access types are encoded to fit into small table cells. #MCU_IOC_MCU_IOC_MAP1_LEGEND shows the codes that are used for access types in this section.

Table 14-29 MCU_IOC Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

14.10.3.1 IOCFG0 Register (Offset = 0h) [Reset = 00006000h]

IOCFG0 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG0_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG0_TABLE.

Return to the Summary Table.

Configuration of DIO0

Figure 14-23 IOCFG0 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-30 IOCFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / outut 7h = OPENSRC_INV : Open Source Inverted input/output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO0 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.2 IOCFG1 Register (Offset = 4h) [Reset = 00006000h]

IOCFG1 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG1_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG1_TABLE.

Return to the Summary Table.

Configuration of DIO1

Figure 14-24 IOCFG1 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-31 IOCFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO1 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.3 IOCFG2 Register (Offset = 8h) [Reset = 00006000h]

IOCFG2 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG2_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG2_TABLE.

Return to the Summary Table.

Configuration of DIO2

Figure 14-25 IOCFG2 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-32 IOCFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO2 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.4 IOCFG3 Register (Offset = Ch) [Reset = 00006000h]

IOCFG3 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG3_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG3_TABLE.

Return to the Summary Table.

Configuration of DIO3

Figure 14-26 IOCFG3 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-33 IOCFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO3 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.5 IOCFG4 Register (Offset = 10h) [Reset = 00006000h]

IOCFG4 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG4_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG4_TABLE.

Return to the Summary Table.

Configuration of DIO4

Figure 14-27 IOCFG4 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-34 IOCFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO4 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.6 IOCFG5 Register (Offset = 14h) [Reset = 00006000h]

IOCFG5 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG5_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG5_TABLE.

Return to the Summary Table.

Configuration of DIO5

Figure 14-28 IOCFG5 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-35 IOCFG5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO5 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.7 IOCFG6 Register (Offset = 18h) [Reset = 00006000h]

IOCFG6 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG6_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG6_TABLE.

Return to the Summary Table.

Configuration of DIO6

Figure 14-29 IOCFG6 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-36 IOCFG6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO6 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.8 IOCFG7 Register (Offset = 1Ch) [Reset = 00006000h]

IOCFG7 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG7_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG7_TABLE.

Return to the Summary Table.

Configuration of DIO7

Figure 14-30 IOCFG7 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-37 IOCFG7 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO7 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.9 IOCFG8 Register (Offset = 20h) [Reset = 00006000h]

IOCFG8 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG8_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG8_TABLE.

Return to the Summary Table.

Configuration of DIO8

Figure 14-31 IOCFG8 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-38 IOCFG8 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO8 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.10 IOCFG9 Register (Offset = 24h) [Reset = 00006000h]

IOCFG9 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG9_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG9_TABLE.

Return to the Summary Table.

Configuration of DIO9

Figure 14-32 IOCFG9 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-39 IOCFG9 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO9 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.11 IOCFG10 Register (Offset = 28h) [Reset = 00006000h]

IOCFG10 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG10_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG10_TABLE.

Return to the Summary Table.

Configuration of DIO10

Figure 14-33 IOCFG10 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-40 IOCFG10 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO10 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.12 IOCFG11 Register (Offset = 2Ch) [Reset = 00006000h]

IOCFG11 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG11_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG11_TABLE.

Return to the Summary Table.

Configuration of DIO11

Figure 14-34 IOCFG11 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-41 IOCFG11 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO11 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.13 IOCFG12 Register (Offset = 30h) [Reset = 00006000h]

IOCFG12 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG12_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG12_TABLE.

Return to the Summary Table.

Configuration of DIO12

Figure 14-35 IOCFG12 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-42 IOCFG12 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO12 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.14 IOCFG13 Register (Offset = 34h) [Reset = 00006000h]

IOCFG13 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG13_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG13_TABLE.

Return to the Summary Table.

Configuration of DIO13

Figure 14-36 IOCFG13 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-43 IOCFG13 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO13 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.15 IOCFG14 Register (Offset = 38h) [Reset = 00006000h]

IOCFG14 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG14_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG14_TABLE.

Return to the Summary Table.

Configuration of DIO14

Figure 14-37 IOCFG14 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-44 IOCFG14 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO14 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.16 IOCFG15 Register (Offset = 3Ch) [Reset = 00006000h]

IOCFG15 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG15_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG15_TABLE.

Return to the Summary Table.

Configuration of DIO15

Figure 14-38 IOCFG15 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-45 IOCFG15 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO15 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.17 IOCFG16 Register (Offset = 40h) [Reset = 00086000h]

IOCFG16 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG16_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG16_TABLE.

Return to the Summary Table.

Configuration of DIO16

Figure 14-39 IOCFG16 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-46 IOCFG16 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO16 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.18 IOCFG17 Register (Offset = 44h) [Reset = 00106000h]

IOCFG17 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG17_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG17_TABLE.

Return to the Summary Table.

Configuration of DIO17

Figure 14-40 IOCFG17 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-47 IOCFG17 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO17 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.19 IOCFG18 Register (Offset = 48h) [Reset = 00006000h]

IOCFG18 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG18_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG18_TABLE.

Return to the Summary Table.

Configuration of DIO18

Figure 14-41 IOCFG18 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-48 IOCFG18 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO18 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.20 IOCFG19 Register (Offset = 4Ch) [Reset = 00006000h]

IOCFG19 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG19_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG19_TABLE.

Return to the Summary Table.

Configuration of DIO19

Figure 14-42 IOCFG19 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-49 IOCFG19 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO19 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.21 IOCFG20 Register (Offset = 50h) [Reset = 00006000h]

IOCFG20 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG20_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG20_TABLE.

Return to the Summary Table.

Configuration of DIO20

Figure 14-43 IOCFG20 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-50 IOCFG20 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO20 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.22 IOCFG21 Register (Offset = 54h) [Reset = 00006000h]

IOCFG21 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG21_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG21_TABLE.

Return to the Summary Table.

Configuration of DIO21

Figure 14-44 IOCFG21 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-51 IOCFG21 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO21 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.23 IOCFG22 Register (Offset = 58h) [Reset = 00006000h]

IOCFG22 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG22_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG22_TABLE.

Return to the Summary Table.

Configuration of DIO22

Figure 14-45 IOCFG22 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-52 IOCFG22 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO22 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.24 IOCFG23 Register (Offset = 5Ch) [Reset = 00006000h]

IOCFG23 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG23_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG23_TABLE.

Return to the Summary Table.

Configuration of DIO23

Figure 14-46 IOCFG23 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-53 IOCFG23 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO23 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.25 IOCFG24 Register (Offset = 60h) [Reset = 00006000h]

IOCFG24 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG24_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG24_TABLE.

Return to the Summary Table.

Configuration of DIO24

Figure 14-47 IOCFG24 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-54 IOCFG24 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO24 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.26 IOCFG25 Register (Offset = 64h) [Reset = 00006000h]

IOCFG25 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG25_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG25_TABLE.

Return to the Summary Table.

Configuration of DIO25

Figure 14-48 IOCFG25 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-55 IOCFG25 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO25 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.27 IOCFG26 Register (Offset = 68h) [Reset = 00006000h]

IOCFG26 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG26_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG26_TABLE.

Return to the Summary Table.

Configuration of DIO26

Figure 14-49 IOCFG26 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-56 IOCFG26 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO26 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.28 IOCFG27 Register (Offset = 6Ch) [Reset = 00006000h]

IOCFG27 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG27_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG27_TABLE.

Return to the Summary Table.

Configuration of DIO27

Figure 14-50 IOCFG27 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-57 IOCFG27 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO27 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.29 IOCFG28 Register (Offset = 70h) [Reset = 00006000h]

IOCFG28 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG28_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG28_TABLE.

Return to the Summary Table.

Configuration of DIO28

Figure 14-51 IOCFG28 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-58 IOCFG28 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO28 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.30 IOCFG29 Register (Offset = 74h) [Reset = 00006000h]

IOCFG29 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG29_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG29_TABLE.

Return to the Summary Table.

Configuration of DIO29

Figure 14-52 IOCFG29 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-59 IOCFG29 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO29 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.31 IOCFG30 Register (Offset = 78h) [Reset = 00006000h]

IOCFG30 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG30_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG30_TABLE.

Return to the Summary Table.

Configuration of DIO30

Figure 14-53 IOCFG30 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-60 IOCFG30 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO30 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In

14.10.3.32 IOCFG31 Register (Offset = 7Ch) [Reset = 00006000h]

IOCFG31 is shown in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG31_FIGURE and described in #MCU_IOC_MCU_IOC_MAP1_MCU_IOC_ALL_IOCFG31_TABLE.

Return to the Summary Table.

Configuration of DIO31

Figure 14-54 IOCFG31 Register

31	30	29	28	27	26	25	24
RESERVED	HYST_EN	IE	WU_CFG		IOMODE
R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
IOEV_AON_PROG2_EN	IOEV_AON_PROG1_EN	IOEV_AON_PROG0_EN	RESERVED		EDGE_IRQ_EN	EDGE_DET
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	PULL_CTL		SLEW_RED	IOCURR		IOSTR
R-0h	R/W-3h		R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
IOEV_RTC_EN	IOEV_MCU_WU_EN	PORT_ID
R/W-0h	R/W-0h	R/W-0h

Table 14-61 IOCFG31 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	HYST_EN	R/W	0h	0: Input hysteresis disable 1: Input hysteresis enable
29	IE	R/W	0h	0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27	WU_CFG	R/W	0h	If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24	IOMODE	R/W	0h	IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output
23	IOEV_AON_PROG2_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event
22	IOEV_AON_PROG1_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event
21	IOEV_AON_PROG0_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event
20-19	RESERVED	R	0h	Reserved
18	EDGE_IRQ_EN	R/W	0h	0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16	EDGE_DET	R/W	0h	Enable generation of edge detection events on this IO 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection
15	RESERVED	R	0h	Reserved
14-13	PULL_CTL	R/W	3h	Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull
12	SLEW_RED	R/W	0h	0: Normal slew rate 1: Enables reduced slew rate in output driver.
11-10	IOCURR	R/W	0h	Selects IO current mode of this IO. 0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
9-8	IOSTR	R/W	0h	Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
7	IOEV_RTC_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event
6	IOEV_MCU_WU_EN	R/W	0h	Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event
5-0	PORT_ID	R/W	0h	Selects usage for DIO31 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SSI0_RX : SSI0 RX Ah = SSI0_TX : SSI0 TX Bh = SSI0_FSS : SSI0 FSS Ch = SSI0_CLK : SSI0 CLK Dh = I2C_MSSDA : I2C Data Eh = I2C_MSSCL : I2C Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In