SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The serial audio interface consists of two or three clock signals and one or two data signals, depending on how the I2S module is used. The clock signals can be generated either internally (by the PRCM module of the CC13x2x7 and CC26x2x7 device platform) or externally (by the audio device or another clock source).
Table 25-1 lists details about the serial audio pin interface.
| CC13x2x7 and CC26x2x7 Pin | Function and Direction | Description |
|---|---|---|
| MCLK (optional) | Master clock output | Master clock for sample conversion in the external audio device. This signal is not used internally by the CC13x2x7 or CC26x2x7 device platform, and hence, will never be an input to the CC13x2x7 or CC26x2x7 device platform. Some external audio devices do not require this signal. |
| BCLK | Bit clock input/output | Bit clock for the WCLK and the AD0 and AD1 signals. This signal is an input when using an external clock source, and it is an output when using the internal clock source. |
| WCLK | Word clock input/output | Sample framing signal that defines the audio sample frequency and the sample word boundaries in the AD0 and AD1 serial data streams. The WCLK frequency is identical to the audio sample frequency. This signal is an input when using an external clock source, and it is an output when using the internal clock source. |
| AD0 AD1 | Serial data input/output | Serial data signals responsible for transferring audio sample words. Each pin can be configured independently as an input, an output, or it can be unused. All pins use the same interface format (for example, LJF). The AD0 and AD1 pins are hereafter referred to as ADx pins. |
The CC13x2x7 and CC26x2x7 device platform cannot dynamically place the ADx pins in a tri-state condition. Therefore, TDM mode is supported for ADx input pins where only external audio devices drive these signals, but TDM mode is not supported for ADx output pins.