To enable and initialize the SSI, perform the following steps:
- Ensure the corresponding power domain is powered up properly. For details, see Section 8.
- Enable the appropriate SSI module in PRCM by writing to the PRCM:SSICLKGR register, the PRCM:SSICLKGS register, and the PRCM:SSICLKGDS register, or by using the DriverLib functions:
PRCMPeripheralRunEnable(uint32_t)
PRCMPeripheralSleepEnable(uint32_t)
PRCMPeripheralDeepSleepEnable(uint32_t)
and then loading the setting to clock controller by writing to PRCM:CLKLOADCTL
or by using the DriverLib function.
PRCMLoadSet().
- Configure the IOC module to route the SSIn_RX, SSIn_TX, SSIn_FSS, and SSIn_CLK functionalities from I/Os to the SSI module. IOCFGn.PORTID must be written to the correct PORTIDs.
For each of the frame formats, the SSI is configured using the following steps:
- Ensure that the SSE bit in the SSI:CR1 register is clear before making any configuration changes.
- Select whether the SSI is a master or slave:
- For master operations, set the SSI:CR1 register to 0x0000 0000.
- For slave mode (output enabled), set the SSI:CR1 register to 0x0000 0004.
- For slave mode (output disabled), set the SSI:CR1 register to 0x0000 000C.
- Configure the clock prescale divisor by writing to the SSI:CPSR register.
- Write the SSI:CR0 register with the following configuration:
- Serial clock rate (SCR)
- Desired clock phase and polarity, if using Motorola SPI mode (SPH and SPO)
- The protocol mode: Motorola SPI, TI SSF, MICROWIRE (FRF)
- The data size (DSS)
- Optionally, configure the μDMA channel (see Section 15) and enable the DMA options in the SSI:DMACR register.
- Enable the SSI by setting the SSE bit in the SSI:CR1 register.
As an example, assume that the SSI configuration
is required to operate with the following parameters:
- Master operation
- Texas Instruments SSI mode
- 1-Mbps bit rate
- 8 data bits
Assuming the system clock is 48 MHz, the bit-rate calculation is shown in Equation 9.
Equation 9. SSIn_CLK = PERDMACLK / [CPSDVSR × (1 + SCR)] 1 × 106 = 20 × 106 / [CPSDVSR × (1 + SCR)] 1000000 bps = 48000000 Hz / [2 × (1 + 23)]
In this case, if CPSDVSR = 0x2, SCR must be 0x18.
The configuration sequence is:
- Ensure that the SSE bit in the SSI:CR1 register is clear.
- Write the SSI:CR1 register with a value of 0x0000 0000.
- Write the SSI:CPSR register with a value of 0x0000 0002.
- Write the SSI:CR0 register with a value of 0x0000 1817.
- The SSI is then enabled by setting the SSE bit in the SSI:CR1 register.