SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The SCE clock source gets emulated when it equals SCLK_MF or SCLK_LF and the MCU domain is active. Clock emulation results in SCE clock period jitter:
The instant SCE clock period jitter equals ±2 SCLK_HF periods.
The instant SCE clock period jitter is 2 SCLK_HF periods. A single SCE clock period increases or decreases by 6 to 8 SCLK_HF periods when emulation starts or ends.
Clock emulation has the following implications: