SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
#RFCORE_IG_RFCPWM_RFCORE_IG_RFCPWM_MAP_RFCPWM_TABLE_1 lists the memory-mapped registers for the RFC_PWR registers. All register offset addresses not listed in #RFCORE_IG_RFCPWM_RFCORE_IG_RFCPWM_MAP_RFCPWM_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0h | PWMCLKEN | RF Core Power Management and Clock Enable | #RFCORE_IG_RFCPWM_RFCORE_IG_RFCPWM_MAP_RFCPWM_RFCORE_IG_RFCPWM_ALL_PWMCLKEN |
Complex bit access types are encoded to fit into small table cells. #RFCORE_IG_RFCPWM_RFCORE_IG_RFCPWM_MAP_RFCPWM_LEGEND shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
PWMCLKEN is shown in #RFCORE_IG_RFCPWM_RFCORE_IG_RFCPWM_MAP_RFCPWM_RFCORE_IG_RFCPWM_ALL_PWMCLKEN_FIGURE and described in #RFCORE_IG_RFCPWM_RFCORE_IG_RFCPWM_MAP_RFCPWM_RFCORE_IG_RFCPWM_ALL_PWMCLKEN_TABLE.
Return to the Summary Table.
RF Core Power Management and Clock Enable
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RFCTRC | FSCA | PHA | ||||
| R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RAT | RFERAM | RFE | MDMRAM | MDM | CPERAM | CPE | RFC |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-1h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-11 | RESERVED | R | 0h | Reserved |
| 10 | RFCTRC | R/W | 0h | Enable clock to the RF Core Tracer (RFCTRC) module. |
| 9 | FSCA | R/W | 0h | Enable clock to the Frequency Synthesizer Calibration Accelerator (FSCA) module. |
| 8 | PHA | R/W | 0h | Enable clock to the Packet Handling Accelerator (PHA) module. |
| 7 | RAT | R/W | 0h | Enable clock to the Radio Timer (RAT) module. |
| 6 | RFERAM | R/W | 0h | Enable clock to the RF Engine RAM module. |
| 5 | RFE | R/W | 0h | Enable clock to the RF Engine (RFE) module. |
| 4 | MDMRAM | R/W | 0h | Enable clock to the Modem RAM module. |
| 3 | MDM | R/W | 0h | Enable clock to the Modem (MDM) module. |
| 2 | CPERAM | R/W | 0h | Enable clock to the Command and Packet Engine (CPE) RAM module. As part of RF Core initialization, set this bit together with CPE bit to enable CPE to boot. |
| 1 | CPE | R/W | 0h | Enable processor clock (hclk) to the Command and Packet Engine (CPE). As part of RF Core initialization, set this bit together with CPERAM bit to enable CPE to boot. |
| 0 | RFC | R | 1h | Enable essential clocks for the RF Core interface. This includes the interconnect, the radio doorbell DBELL command interface, the power management (PWR) clock control module, and bus clock (sclk) for the CPE. To remove possibility of locking yourself out from the RF Core, this bit can not be cleared. If you need to disable all clocks to the RF Core, see the PRCM:RFCCLKG.CLK_EN register. |