SWCU192 November   2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

 

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    9.     402
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  14.   404
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    4.     448
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    5.     454
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  16.   456
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    3.     459
      1.      460
      2.      461
        1.       462
        2.       463
        3.       464
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        5.       466
      3.      467
      4.      468
    4.     469
      1.      470
      2.      471
      3.      472
      4.      473
      5.      474
    5.     475
      1.      476
  17.   477
    1.     478
    2.     479
      1.      480
      2.      481
      3.      482
        1.       483
      4.      484
    3.     485
      1.      486
      2.      487
      3.      488
    4.     489
      1.      490
  18.   491
    1.     492
    2.     493
    3.     494
    4.     495
      1.      496
  19.   497
    1.     498
    2.     499
    3.     500
    4.     501
    5.     502
      1.      503
      2.      504
      3.      505
    6.     506
      1.      507
        1.       508
        2.       509
        3.       510
          1.        511
          2.        512
    7.     513
      1.      514
  20.   515
    1.     516
      1.      517
    2.     518
      1.      519
        1.       520
      2.      521
        1.       522
        2.       523
      3.      524
      4.      525
    3.     526
      1.      527
        1.       528
        2.       529
        3.       530
        4.       531
      2.      532
        1.       533
          1.        534
        2.       535
          1.        536
          2.        537
        3.       538
          1.        539
        4.       540
          1.        541
          2.        542
          3.        543
        5.       544
        6.       545
        7.       546
        8.       547
        9.       548
        10.       549
    4.     550
      1.      551
        1.       552
      2.      553
        1.       554
        2.       555
          1.        556
          2.        557
          3.        558
          4.        559
          5.        560
      3.      561
        1.       562
        2.       563
        3.       564
      4.      565
        1.       566
        2.       567
          1.        568
          2.        569
          3.        570
      5.      571
        1.       572
        2.       573
          1.        574
          2.        575
          3.        576
          4.        577
            1.         578
            2.         579
          5.        580
          6.        581
        3.       582
          1.        583
          2.        584
          3.        585
            1.         586
            2.         587
            3.         588
            4.         589
          4.        590
      6.      591
        1.       592
        2.       593
      7.      594
        1.       595
        2.       596
          1.        597
          2.        598
          3.        599
          4.        600
          5.        601
            1.         602
              1.          603
            2.         604
              1.          605
            3.         606
              1.          607
          6.        608
    5.     609
      1.      610
        1.       611
        2.       612
      2.      613
        1.       614
        2.       615
          1.        616
          2.        617
          3.        618
          4.        619
          5.        620
          6.        621
          7.        622
          8.        623
      3.      624
        1.       625
        2.       626
          1.        627
          2.        628
          3.        629
          4.        630
      4.      631
        1.       632
        2.       633
          1.        634
          2.        635
          3.        636
            1.         637
            2.         638
      5.      639
        1.       640
        2.       641
          1.        642
          2.        643
          3.        644
            1.         645
            2.         646
            3.         647
          4.        648
            1.         649
            2.         650
            3.         651
            4.         652
          5.        653
          6.        654
      6.      655
        1.       656
        2.       657
          1.        658
          2.        659
          3.        660
          4.        661
          5.        662
    6.     663
      1.      664
        1.       665
        2.       666
          1.        667
            1.         668
            2.         669
      2.      670
      3.      671
      4.      672
      5.      673
      6.      674
      7.      675
    7.     676
    8.     677
      1.      678
      2.      679
      3.      680
      4.      681
      5.      682
      6.      683
      7.      684
      8.      685
      9.      686
      10.      687
      11.      688
      12.      689
  21.   690
    1.     691
    2.     692
    3.     693
      1.      694
  22.   695
    1.     696
    2.     697
    3.     698
    4.     699
      1.      700
      2.      701
      3.      702
      4.      703
        1.       704
        2.       705
          1.        706
          2.        707
      5.      708
      6.      709
      7.      710
    5.     711
    6.     712
    7.     713
      1.      714
  23.   715
    1.     716
    2.     717
    3.     718
    4.     719
      1.      720
      2.      721
        1.       722
        2.       723
      3.      724
      4.      725
        1.       726
        2.       727
          1.        728
          2.        729
        3.       730
        4.       731
        5.       732
        6.       733
        7.       734
    5.     735
    6.     736
    7.     737
      1.      738
  24.   739
    1.     740
    2.     741
    3.     742
      1.      743
        1.       744
        2.       745
        3.       746
        4.       747
        5.       748
      2.      749
        1.       750
      3.      751
        1.       752
        2.       753
      4.      754
      5.      755
        1.       756
        2.       757
    4.     758
    5.     759
      1.      760
  25.   761
    1.     762
    2.     763
    3.     764
    4.     765
      1.      766
        1.       767
      2.      768
      3.      769
      4.      770
        1.       771
      5.      772
        1.       773
      6.      774
        1.       775
      7.      776
        1.       777
      8.      778
        1.       779
        2.       780
    5.     781
      1.      782
      2.      783
      3.      784
      4.      785
        1.       786
        2.       787
        3.       788
    6.     789
      1.      790
      2.      791
      3.      792
      4.      793
    7.     794
    8.     795
      1.      796
      2.      797
    9.     798
      1.      799
  26.   800
    1.     801
      1.      802
    2.     803
      1.      804
      2.      805
      3.      806
        1.       807
        2.       808
        3.       809
      4.      810
        1.       811
        2.       812
        3.       813
    3.     814
      1.      815
      2.      816
        1.       817
        2.       818
        3.       819
        4.       820
        5.       821
          1.        822
          2.        823
          3.        824
        6.       825
          1.        826
        7.       827
          1.        828
          2.        829
          3.        830
          4.        831
        8.       832
      3.      833
        1.       834
          1.        835
          2.        836
          3.        837
          4.        838
          5.        839
          6.        840
          7.        841
          8.        842
          9.        843
          10.        844
          11.        845
          12.        846
          13.        847
          14.        848
        2.       849
          1.        850
          2.        851
          3.        852
          4.        853
          5.        854
          6.        855
          7.        856
          8.        857
          9.        858
          10.        859
          11.        860
          12.        861
          13.        862
          14.        863
          15.        864
          16.        865
          17.        866
          18.        867
          19.        868
          20.        869
      4.      870
        1.       871
        2.       872
        3.       873
        4.       874
        5.       875
    4.     876
      1.      877
        1.       878
        2.       879
        3.       880
        4.       881
        5.       882
      2.      883
        1.       884
        2.       885
    5.     886
      1.      887
        1.       888
        2.       889
        3.       890
        4.       891
      2.      892
      3.      893
        1.       894
        2.       895
      4.      896
        1.       897
          1.        898
            1.         899
            2.         900
          2.        901
          3.        902
          4.        903
          5.        904
        2.       905
        3.       906
        4.       907
        5.       908
        6.       909
      5.      910
        1.       911
        2.       912
        3.       913
        4.       914
        5.       915
        6.       916
    6.     917
      1.      918
        1.       919
          1.        920
        2.       921
        3.       922
        4.       923
      2.      924
    7.     925
      1.      926
      2.      927
    8.     928
      1.      929
      2.      930
      3.      931
      4.      932
      5.      933
      6.      934
      7.      935
      8.      936
        1.       937
        2.       938
        3.       939
        4.       940
      9.      941
        1.       942
        2.       943
        3.       944
      10.      945
        1.       946
        2.       947
        3.       948
        4.       949
        5.       950
      11.      951
        1.       952
        2.       953
        3.       954
        4.       955
        5.       956
      12.      957
      13.      958
      14.      959
      15.      960
      16.      961
      17.      962
    9.     963
      1.      964
    10.     965
      1.      966
      2.      967
        1.       968
          1.        969
        2.       970
        3.       971
      3.      972
      4.      973
        1.       974
        2.       975
      5.      976
        1.       977
        2.       978
          1.        979
        3.       980
          1.        981
          2.        982
        4.       983
          1.        984
          2.        985
        5.       986
          1.        987
          2.        988
          3.        989
      6.      990
        1.       991
        2.       992
    11.     993
      1.      994
      2.      995
      3.      996
  27.   997

25.9.1 I2S Registers

#I2S_I2S_MAP1_TABLE_1 lists the memory-mapped registers for the I2S registers. All register offset addresses not listed in #I2S_I2S_MAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 25-2 I2S Registers
Offset Acronym Register Name Section
0h AIFWCLKSRC WCLK Source Selection #I2S_I2S_MAP1_I2S_ALL_AIFWCLKSRC
4h AIFDMACFG DMA Buffer Size Configuration #I2S_I2S_MAP1_I2S_ALL_AIFDMACFG
8h AIFDIRCFG Pin Direction #I2S_I2S_MAP1_I2S_ALL_AIFDIRCFG
Ch AIFFMTCFG Serial Interface Format Configuration #I2S_I2S_MAP1_I2S_ALL_AIFFMTCFG
10h AIFWMASK0 Word Selection Bit Mask for Pin 0 #I2S_I2S_MAP1_I2S_ALL_AIFWMASK0
14h AIFWMASK1 Word Selection Bit Mask for Pin 1 #I2S_I2S_MAP1_I2S_ALL_AIFWMASK1
1Ch AIFPWMVALUE Audio Interface PWM Debug Value #I2S_I2S_MAP1_I2S_ALL_AIFPWMVALUE
20h AIFINPTRNEXT DMA Input Buffer Next Pointer #I2S_I2S_MAP1_I2S_ALL_AIFINPTRNEXT
24h AIFINPTR DMA Input Buffer Current Pointer #I2S_I2S_MAP1_I2S_ALL_AIFINPTR
28h AIFOUTPTRNEXT DMA Output Buffer Next Pointer #I2S_I2S_MAP1_I2S_ALL_AIFOUTPTRNEXT
2Ch AIFOUTPTR DMA Output Buffer Current Pointer #I2S_I2S_MAP1_I2S_ALL_AIFOUTPTR
34h STMPCTL Samplestamp Generator Control Register #I2S_I2S_MAP1_I2S_ALL_STMPCTL
38h STMPXCNTCAPT0 Captured XOSC Counter Value, Capture Channel 0 #I2S_I2S_MAP1_I2S_ALL_STMPXCNTCAPT0
3Ch STMPXPER XOSC Period Value #I2S_I2S_MAP1_I2S_ALL_STMPXPER
40h STMPWCNTCAPT0 Captured WCLK Counter Value, Capture Channel 0 #I2S_I2S_MAP1_I2S_ALL_STMPWCNTCAPT0
44h STMPWPER WCLK Counter Period Value #I2S_I2S_MAP1_I2S_ALL_STMPWPER
48h STMPINTRIG WCLK Counter Trigger Value for Input Pins #I2S_I2S_MAP1_I2S_ALL_STMPINTRIG
4Ch STMPOUTTRIG WCLK Counter Trigger Value for Output Pins #I2S_I2S_MAP1_I2S_ALL_STMPOUTTRIG
50h STMPWSET WCLK Counter Set Operation #I2S_I2S_MAP1_I2S_ALL_STMPWSET
54h STMPWADD WCLK Counter Add Operation #I2S_I2S_MAP1_I2S_ALL_STMPWADD
58h STMPXPERMIN XOSC Minimum Period Value #I2S_I2S_MAP1_I2S_ALL_STMPXPERMIN
5Ch STMPWCNT Current Value of WCNT #I2S_I2S_MAP1_I2S_ALL_STMPWCNT
60h STMPXCNT Current Value of XCNT #I2S_I2S_MAP1_I2S_ALL_STMPXCNT
64h STMPXCNTCAPT1 Internal #I2S_I2S_MAP1_I2S_ALL_STMPXCNTCAPT1
68h STMPWCNTCAPT1 Internal #I2S_I2S_MAP1_I2S_ALL_STMPWCNTCAPT1
70h IRQMASK Interrupt Mask Register #I2S_I2S_MAP1_I2S_ALL_IRQMASK
74h IRQFLAGS Raw Interrupt Status Register #I2S_I2S_MAP1_I2S_ALL_IRQFLAGS
78h IRQSET Interrupt Set Register #I2S_I2S_MAP1_I2S_ALL_IRQSET
7Ch IRQCLR Interrupt Clear Register #I2S_I2S_MAP1_I2S_ALL_IRQCLR

Complex bit access types are encoded to fit into small table cells. #I2S_I2S_MAP1_LEGEND shows the codes that are used for access types in this section.

Table 25-3 I2S Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

25.9.1.1 AIFWCLKSRC Register (Offset = 0h) [Reset = 00000000h]

AIFWCLKSRC is shown in #I2S_I2S_MAP1_I2S_ALL_AIFWCLKSRC_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_AIFWCLKSRC_TABLE.

Return to the Summary Table.

WCLK Source Selection

Figure 25-12 AIFWCLKSRC Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED WCLK_INV WCLK_SRC
R-0h R/W-0h R/W-0h
Table 25-4 AIFWCLKSRC Register Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R 0h Reserved
2 WCLK_INV R/W 0h Inverts WCLK source (pad or internal) when set.
0: Not inverted
1: Inverted
1-0 WCLK_SRC R/W 0h Selects WCLK source for AIF (should be the same as the BCLK source). The BCLK source is defined in the PRCM:I2SBCLKSEL.SRC

0h = None ('0')

1h = External WCLK generator, from pad

2h = Internal WCLK generator, from module PRCM

3h = Not supported. Will give same WCLK as 'NONE' ('00')

25.9.1.2 AIFDMACFG Register (Offset = 4h) [Reset = 00000000h]

AIFDMACFG is shown in #I2S_I2S_MAP1_I2S_ALL_AIFDMACFG_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_AIFDMACFG_TABLE.

Return to the Summary Table.

DMA Buffer Size Configuration

Figure 25-13 AIFDMACFG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED END_FRAME_IDX
R-0h R/W-0h
Table 25-5 AIFDMACFG Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h Reserved
7-0 END_FRAME_IDX R/W 0h Defines the length of the DMA buffer. Writing a non-zero value to this register field enables and initializes AIF. Note that before doing so, all other configuration must have been done, and AIFINPTRNEXT/AIFOUTPTRNEXT must have been loaded.

25.9.1.3 AIFDIRCFG Register (Offset = 8h) [Reset = 00000000h]

AIFDIRCFG is shown in #I2S_I2S_MAP1_I2S_ALL_AIFDIRCFG_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_AIFDIRCFG_TABLE.

Return to the Summary Table.

Pin Direction

Figure 25-14 AIFDIRCFG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED AD1 RESERVED AD0
R-0h R/W-0h R-0h R/W-0h
Table 25-6 AIFDIRCFG Register Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h Reserved
5-4 AD1 R/W 0h Configures the AD1 audio data pin usage:
0x3: Reserved

0h = Not in use (disabled)

1h = Input mode

2h = Output mode

3-2 RESERVED R 0h Reserved
1-0 AD0 R/W 0h Configures the AD0 audio data pin usage:
0x3: Reserved

0h = Not in use (disabled)

1h = Input mode

2h = Output mode

25.9.1.4 AIFFMTCFG Register (Offset = Ch) [Reset = 00000170h]

AIFFMTCFG is shown in #I2S_I2S_MAP1_I2S_ALL_AIFFMTCFG_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_AIFFMTCFG_TABLE.

Return to the Summary Table.

Serial Interface Format Configuration

Figure 25-15 AIFFMTCFG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
DATA_DELAY
R/W-1h
7 6 5 4 3 2 1 0
MEM_LEN_24 SMPL_EDGE DUAL_PHASE WORD_LEN
R/W-0h R/W-1h R/W-1h R/W-10h
Table 25-7 AIFFMTCFG Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 DATA_DELAY R/W 1h The number of BCLK periods between a WCLK edge and MSB of the first word in a phase:
0x00: LJF and DSP format
0x01: I2S and DSP format
0x02: RJF format
...
0xFF: RJF format
Note: When 0, MSB of the next word will be output in the idle period between LSB of the previous word and the start of the next word. Otherwise logical 0 will be output until the data delay has expired.
7 MEM_LEN_24 R/W 0h The size of each word stored to or loaded from memory:

0h = 16BIT : 16-bit (one 16 bit access per sample)

1h = 24BIT : 24-bit (one 8 bit and one 16 bit locked access per sample)

6 SMPL_EDGE R/W 1h On the serial audio interface, data (and wclk) is sampled and clocked out on opposite edges of BCLK.

0h = Data is sampled on the negative edge and clocked out on the positive edge.

1h = Data is sampled on the positive edge and clocked out on the negative edge.

5 DUAL_PHASE R/W 1h Selects dual- or single-phase format.
0: Single-phase: DSP format
1: Dual-phase: I2S, LJF and RJF formats
4-0 WORD_LEN R/W 10h Number of bits per word (8-24):
In single-phase format, this is the exact number of bits per word.
In dual-phase format, this is the maximum number of bits per word.
Values below 8 and above 24 give undefined behavior. Data written to memory is always aligned to 16 or 24 bits as defined by MEM_LEN_24. Bit widths that differ from this alignment will either be truncated or zero padded.

25.9.1.5 AIFWMASK0 Register (Offset = 10h) [Reset = 00000003h]

AIFWMASK0 is shown in #I2S_I2S_MAP1_I2S_ALL_AIFWMASK0_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_AIFWMASK0_TABLE.

Return to the Summary Table.

Word Selection Bit Mask for Pin 0

Figure 25-16 AIFWMASK0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED MASK
R-0h R/W-3h
Table 25-8 AIFWMASK0 Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h Reserved
7-0 MASK R/W 3h Bit-mask indicating valid channels in a frame on AD0.
In single-phase mode, each bit represents one channel, starting with LSB for the first word in the frame. A frame can contain up to 8 channels. Channels that are not included in the mask will not be sampled and stored in memory, and clocked out as '0'.
In dual-phase mode, only the two LSBs are considered. For a stereo configuration, set both bits. For a mono configuration, set bit 0 only. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated when clocked out.
In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated in the second phase when clocked out.
If all bits are zero, no input words will be stored to memory, and the output data lines will be constant '0'. This can be utilized when PWM debug output is desired without any actively used output pins.

25.9.1.6 AIFWMASK1 Register (Offset = 14h) [Reset = 00000003h]

AIFWMASK1 is shown in #I2S_I2S_MAP1_I2S_ALL_AIFWMASK1_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_AIFWMASK1_TABLE.

Return to the Summary Table.

Word Selection Bit Mask for Pin 1

Figure 25-17 AIFWMASK1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED MASK
R-0h R/W-3h
Table 25-9 AIFWMASK1 Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h Reserved
7-0 MASK R/W 3h Bit-mask indicating valid channels in a frame on AD1.
In single-phase mode, each bit represents one channel, starting with LSB for the first word in the frame. A frame can contain up to 8 channels. Channels that are not included in the mask will not be sampled and stored in memory, and clocked out as '0'.
In dual-phase mode, only the two LSBs are considered. For a stereo configuration, set both bits. For a mono configuration, set bit 0 only. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated when clocked out.
In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated in the second phase when clocked out.
If all bits are zero, no input words will be stored to memory, and the output data lines will be constant '0'. This can be utilized when PWM debug output is desired without any actively used output pins.

25.9.1.7 AIFPWMVALUE Register (Offset = 1Ch) [Reset = 00000000h]

AIFPWMVALUE is shown in #I2S_I2S_MAP1_I2S_ALL_AIFPWMVALUE_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_AIFPWMVALUE_TABLE.

Return to the Summary Table.

Audio Interface PWM Debug Value

Figure 25-18 AIFPWMVALUE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PULSE_WIDTH
R-0h R/W-0h
Table 25-10 AIFPWMVALUE Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 PULSE_WIDTH R/W 0h The value written to this register determines the width of the active high PWM pulse (pwm_debug), which starts together with MSB of the first output word in a DMA buffer:
0x0000: Constant low
0x0001: Width of the pulse (number of BCLK cycles, here 1).
...
0xFFFE: Width of the pulse (number of BCLK cycles, here 65534).
0xFFFF: Constant high

25.9.1.8 AIFINPTRNEXT Register (Offset = 20h) [Reset = 00000000h]

AIFINPTRNEXT is shown in #I2S_I2S_MAP1_I2S_ALL_AIFINPTRNEXT_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_AIFINPTRNEXT_TABLE.

Return to the Summary Table.

DMA Input Buffer Next Pointer

Figure 25-19 AIFINPTRNEXT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTR
R/W-0h
Table 25-11 AIFINPTRNEXT Register Field Descriptions
Bit Field Type Reset Description
31-0 PTR R/W 0h Pointer to the first byte in the next DMA input buffer.
The read value equals the last written value until the currently used DMA input buffer is completed, and then becomes null when the last written value is transferred to the DMA controller to start on the next buffer. This event is signalized by IRQFLAGS.AIF_DMA_IN.
At startup, the value must be written once before and once after configuring the DMA buffer size in AIFDMACFG.
The next pointer must be written to this register while the DMA function uses the previously written pointer. If not written in time, IRQFLAGS.PTR_ERR will be raised and all input pins will be disabled.

25.9.1.9 AIFINPTR Register (Offset = 24h) [Reset = 00000000h]

AIFINPTR is shown in #I2S_I2S_MAP1_I2S_ALL_AIFINPTR_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_AIFINPTR_TABLE.

Return to the Summary Table.

DMA Input Buffer Current Pointer

Figure 25-20 AIFINPTR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTR
R-0h
Table 25-12 AIFINPTR Register Field Descriptions
Bit Field Type Reset Description
31-0 PTR R 0h Value of the DMA input buffer pointer currently used by the DMA controller. Incremented by 1 (byte) or 2 (word) for each AHB access.

25.9.1.10 AIFOUTPTRNEXT Register (Offset = 28h) [Reset = 00000000h]

AIFOUTPTRNEXT is shown in #I2S_I2S_MAP1_I2S_ALL_AIFOUTPTRNEXT_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_AIFOUTPTRNEXT_TABLE.

Return to the Summary Table.

DMA Output Buffer Next Pointer

Figure 25-21 AIFOUTPTRNEXT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTR
R/W-0h
Table 25-13 AIFOUTPTRNEXT Register Field Descriptions
Bit Field Type Reset Description
31-0 PTR R/W 0h Pointer to the first byte in the next DMA output buffer.
The read value equals the last written value until the currently used DMA output buffer is completed, and then becomes null when the last written value is transferred to the DMA controller to start on the next buffer. This event is signalized by IRQFLAGS.AIF_DMA_OUT.
At startup, the value must be written once before and once after configuring the DMA buffer size in AIFDMACFG. At this time, the first two samples will be fetched from memory.
The next pointer must be written to this register while the DMA function uses the previously written pointer. If not written in time, IRQFLAGS.PTR_ERR will be raised and all output pins will be disabled.

25.9.1.11 AIFOUTPTR Register (Offset = 2Ch) [Reset = 00000000h]

AIFOUTPTR is shown in #I2S_I2S_MAP1_I2S_ALL_AIFOUTPTR_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_AIFOUTPTR_TABLE.

Return to the Summary Table.

DMA Output Buffer Current Pointer

Figure 25-22 AIFOUTPTR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTR
R-0h
Table 25-14 AIFOUTPTR Register Field Descriptions
Bit Field Type Reset Description
31-0 PTR R 0h Value of the DMA output buffer pointer currently used by the DMA controller Incremented by 1 (byte) or 2 (word) for each AHB access.

25.9.1.12 STMPCTL Register (Offset = 34h) [Reset = 00000000h]

STMPCTL is shown in #I2S_I2S_MAP1_I2S_ALL_STMPCTL_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_STMPCTL_TABLE.

Return to the Summary Table.

Samplestamp Generator Control Register

Figure 25-23 STMPCTL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED OUT_RDY IN_RDY STMP_EN
R-0h R-0h R-0h R/W-0h
Table 25-15 STMPCTL Register Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R 0h Reserved
2 OUT_RDY R 0h Low until the output pins are ready to be started by the samplestamp generator. When started (that is STMPOUTTRIG equals the WCLK counter) the bit goes back low.
1 IN_RDY R 0h Low until the input pins are ready to be started by the samplestamp generator. When started (that is STMPINTRIG equals the WCLK counter) the bit goes back low.
0 STMP_EN R/W 0h Enables the samplestamp generator. The samplestamp generator must only be enabled after it has been properly configured.
When cleared, all samplestamp generator counters and capture values are cleared.

25.9.1.13 STMPXCNTCAPT0 Register (Offset = 38h) [Reset = 00000000h]

STMPXCNTCAPT0 is shown in #I2S_I2S_MAP1_I2S_ALL_STMPXCNTCAPT0_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_STMPXCNTCAPT0_TABLE.

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Captured XOSC Counter Value, Capture Channel 0

Figure 25-24 STMPXCNTCAPT0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CAPT_VALUE
R-0h R-0h
Table 25-16 STMPXCNTCAPT0 Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 CAPT_VALUE R 0h The value of the samplestamp XOSC counter (STMPXCNT.CURR_VALUE) last time an event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for channel 0). This number corresponds to the number of 24 MHz clock cycles since the last positive edge of the selected WCLK.
The value is cleared when STMPCTL.STMP_EN = 0.
Note: Due to buffering and synchronization, WCLK is delayed by a small number of BCLK periods and clk periods.
Note: When calculating the fractional part of the sample stamp, STMPXPER may be less than this bit field.

25.9.1.14 STMPXPER Register (Offset = 3Ch) [Reset = 00000000h]

STMPXPER is shown in #I2S_I2S_MAP1_I2S_ALL_STMPXPER_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_STMPXPER_TABLE.

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XOSC Period Value

Figure 25-25 STMPXPER Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED VALUE
R-0h R-0h
Table 25-17 STMPXPER Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 VALUE R 0h The number of 24 MHz clock cycles in the previous WCLK period (that is - the next value of the XOSC counter at the positive WCLK edge, had it not been reset to 0).
The value is cleared when STMPCTL.STMP_EN = 0.

25.9.1.15 STMPWCNTCAPT0 Register (Offset = 40h) [Reset = 00000000h]

STMPWCNTCAPT0 is shown in #I2S_I2S_MAP1_I2S_ALL_STMPWCNTCAPT0_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_STMPWCNTCAPT0_TABLE.

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Captured WCLK Counter Value, Capture Channel 0

Figure 25-26 STMPWCNTCAPT0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CAPT_VALUE
R-0h R-0h
Table 25-18 STMPWCNTCAPT0 Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 CAPT_VALUE R 0h The value of the samplestamp WCLK counter (STMPWCNT.CURR_VALUE) last time an event was pulsed (event source selected in EVENT:I2SSTMPSEL0.EV for channel 0). This number corresponds to the number of positive WCLK edges since the samplestamp generator was enabled (not taking modification through STMPWADD/STMPWSET into account).
The value is cleared when STMPCTL.STMP_EN = 0.

25.9.1.16 STMPWPER Register (Offset = 44h) [Reset = 00000000h]

STMPWPER is shown in #I2S_I2S_MAP1_I2S_ALL_STMPWPER_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_STMPWPER_TABLE.

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WCLK Counter Period Value

Figure 25-27 STMPWPER Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED VALUE
R-0h R/W-0h
Table 25-19 STMPWPER Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 VALUE R/W 0h Used to define when STMPWCNT is to be reset so number of WCLK edges are found for the size of the sample buffer. This is thus a modulo value for the WCLK counter. This number must correspond to the size of the sample buffer used by the system (that is the index of the last sample plus 1).

25.9.1.17 STMPINTRIG Register (Offset = 48h) [Reset = 00000000h]

STMPINTRIG is shown in #I2S_I2S_MAP1_I2S_ALL_STMPINTRIG_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_STMPINTRIG_TABLE.

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WCLK Counter Trigger Value for Input Pins

Figure 25-28 STMPINTRIG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED IN_START_WCNT
R-0h R/W-0h
Table 25-20 STMPINTRIG Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 IN_START_WCNT R/W 0h Compare value used to start the incoming audio streams.
This bit field shall equal the WCLK counter value during the WCLK period in which the first input word(s) are sampled and stored to memory (that is the sample at the start of the very first DMA input buffer).
The value of this register takes effect when the following conditions are met:
- One or more pins are configured as inputs in AIFDIRCFG.
- AIFDMACFG has been configured for the correct buffer size, and at least 32 BCLK cycle ticks have happened.
Note: To avoid false triggers, this bit field should be set higher than STMPWPER.VALUE.

25.9.1.18 STMPOUTTRIG Register (Offset = 4Ch) [Reset = 00000000h]

STMPOUTTRIG is shown in #I2S_I2S_MAP1_I2S_ALL_STMPOUTTRIG_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_STMPOUTTRIG_TABLE.

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WCLK Counter Trigger Value for Output Pins

Figure 25-29 STMPOUTTRIG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED OUT_START_WCNT
R-0h R/W-0h
Table 25-21 STMPOUTTRIG Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 OUT_START_WCNT R/W 0h Compare value used to start the outgoing audio streams.
This bit field must equal the WCLK counter value during the WCLK period in which the first output word(s) read from memory are clocked out (that is the sample at the start of the very first DMA output buffer).
The value of this register takes effect when the following conditions are met:
- One or more pins are configured as outputs in AIFDIRCFG.
- AIFDMACFG has been configured for the correct buffer size, and 32 BCLK cycle ticks have happened.
- 2 samples have been preloaded from memory (examine the AIFOUTPTR register if necessary).
Note: The memory read access is only performed when required, that is channels 0/1 must be selected in AIFWMASK0/AIFWMASK1.
Note: To avoid false triggers, this bit field should be set higher than STMPWPER.VALUE.

25.9.1.19 STMPWSET Register (Offset = 50h) [Reset = 00000000h]

STMPWSET is shown in #I2S_I2S_MAP1_I2S_ALL_STMPWSET_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_STMPWSET_TABLE.

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WCLK Counter Set Operation

Figure 25-30 STMPWSET Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED VALUE
R-0h R/W-0h
Table 25-22 STMPWSET Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 VALUE R/W 0h WCLK counter modification: Sets the running WCLK counter equal to the written value.

25.9.1.20 STMPWADD Register (Offset = 54h) [Reset = 00000000h]

STMPWADD is shown in #I2S_I2S_MAP1_I2S_ALL_STMPWADD_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_STMPWADD_TABLE.

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WCLK Counter Add Operation

Figure 25-31 STMPWADD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED VALUE_INC
R-0h R/W-0h
Table 25-23 STMPWADD Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 VALUE_INC R/W 0h WCLK counter modification: Adds the written value to the running WCLK counter. If a positive edge of WCLK occurs at the same time as the operation, this will be taken into account.
To add a negative value, write "STMPWPER.VALUE - value".

25.9.1.21 STMPXPERMIN Register (Offset = 58h) [Reset = 0000FFFFh]

STMPXPERMIN is shown in #I2S_I2S_MAP1_I2S_ALL_STMPXPERMIN_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_STMPXPERMIN_TABLE.

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XOSC Minimum Period Value
Minimum Value of STMPXPER

Figure 25-32 STMPXPERMIN Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED VALUE
R-0h R/W-FFFFh
Table 25-24 STMPXPERMIN Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 VALUE R/W FFFFh Each time STMPXPER is updated, the value is also loaded into this register, provided that the value is smaller than the current value in this register.
When written, the register is reset to 0xFFFF (65535), regardless of the value written.
The minimum value can be used to detect extra WCLK pulses (this registers value will be significantly smaller than STMPXPER.VALUE).

25.9.1.22 STMPWCNT Register (Offset = 5Ch) [Reset = 00000000h]

STMPWCNT is shown in #I2S_I2S_MAP1_I2S_ALL_STMPWCNT_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_STMPWCNT_TABLE.

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Current Value of WCNT

Figure 25-33 STMPWCNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CURR_VALUE
R-0h R-0h
Table 25-25 STMPWCNT Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 CURR_VALUE R 0h Current value of the WCLK counter

25.9.1.23 STMPXCNT Register (Offset = 60h) [Reset = 00000000h]

STMPXCNT is shown in #I2S_I2S_MAP1_I2S_ALL_STMPXCNT_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_STMPXCNT_TABLE.

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Current Value of XCNT

Figure 25-34 STMPXCNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CURR_VALUE
R-0h R-0h
Table 25-26 STMPXCNT Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 CURR_VALUE R 0h Current value of the XOSC counter, latched when reading STMPWCNT.

25.9.1.24 STMPXCNTCAPT1 Register (Offset = 64h) [Reset = 00000000h]

STMPXCNTCAPT1 is shown in #I2S_I2S_MAP1_I2S_ALL_STMPXCNTCAPT1_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_STMPXCNTCAPT1_TABLE.

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Internal. Only to be used through TI provided API.

Figure 25-35 STMPXCNTCAPT1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CAPT_VALUE
R-0h R-0h
Table 25-27 STMPXCNTCAPT1 Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 CAPT_VALUE R 0h Internal. Only to be used through TI provided API.

25.9.1.25 STMPWCNTCAPT1 Register (Offset = 68h) [Reset = 00000000h]

STMPWCNTCAPT1 is shown in #I2S_I2S_MAP1_I2S_ALL_STMPWCNTCAPT1_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_STMPWCNTCAPT1_TABLE.

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Internal. Only to be used through TI provided API.

Figure 25-36 STMPWCNTCAPT1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CAPT_VALUE
R-0h R-0h
Table 25-28 STMPWCNTCAPT1 Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 CAPT_VALUE R 0h Internal. Only to be used through TI provided API.

25.9.1.26 IRQMASK Register (Offset = 70h) [Reset = 00000000h]

IRQMASK is shown in #I2S_I2S_MAP1_I2S_ALL_IRQMASK_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_IRQMASK_TABLE.

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Interrupt Mask Register
Selects mask states of the flags in IRQFLAGS that contribute to the I2S_IRQ event.

Figure 25-37 IRQMASK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED AIF_DMA_IN AIF_DMA_OUT WCLK_TIMEOUT BUS_ERR WCLK_ERR PTR_ERR
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 25-29 IRQMASK Register Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h Reserved
5 AIF_DMA_IN R/W 0h IRQFLAGS.AIF_DMA_IN interrupt mask
0: Disable
1: Enable
4 AIF_DMA_OUT R/W 0h IRQFLAGS.AIF_DMA_OUT interrupt mask
0: Disable
1: Enable
3 WCLK_TIMEOUT R/W 0h IRQFLAGS.WCLK_TIMEOUT interrupt mask
0: Disable
1: Enable
2 BUS_ERR R/W 0h IRQFLAGS.BUS_ERR interrupt mask
0: Disable
1: Enable
1 WCLK_ERR R/W 0h IRQFLAGS.WCLK_ERR interrupt mask
0: Disable
1: Enable
0 PTR_ERR R/W 0h IRQFLAGS.PTR_ERR interrupt mask.
0: Disable
1: Enable

25.9.1.27 IRQFLAGS Register (Offset = 74h) [Reset = 00000000h]

IRQFLAGS is shown in #I2S_I2S_MAP1_I2S_ALL_IRQFLAGS_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_IRQFLAGS_TABLE.

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Raw Interrupt Status Register

Figure 25-38 IRQFLAGS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED AIF_DMA_IN AIF_DMA_OUT WCLK_TIMEOUT BUS_ERR WCLK_ERR PTR_ERR
R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 25-30 IRQFLAGS Register Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h Reserved
5 AIF_DMA_IN R 0h Set when condition for this bit field event occurs (auto cleared when input pointer is updated - AIFINPTRNEXT), see description of AIFINPTRNEXT register for details.
4 AIF_DMA_OUT R 0h Set when condition for this bit field event occurs (auto cleared when output pointer is updated - AIFOUTPTRNEXT), see description of AIFOUTPTRNEXT register for details
3 WCLK_TIMEOUT R 0h Set when the sample stamp generator does not detect a positive WCLK edge for 65535 clk periods. This signalizes that the internal or external BCLK and WCLK generator source has been disabled.
The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.WCLK_TIMEOUT).
2 BUS_ERR R 0h Set when a DMA operation is not completed in time (that is audio output buffer underflow, or audio input buffer overflow).
This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.BUS_ERR).
Note that DMA initiated transactions to illegal addresses will not trigger an interrupt. The response to such transactions is undefined.
1 WCLK_ERR R 0h Set when:
- An unexpected WCLK edge occurs during the data delay period of a phase. Note unexpected WCLK edges during the word and idle periods of the phase are not detected.
- In dual-phase mode, when two WCLK edges are less than 4 BCLK cycles apart.
- In single-phase mode, when a WCLK pulse occurs before the last channel.
This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.WCLK_ERR).
0 PTR_ERR R 0h Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been loaded with the next block address in time.
This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.PTR_ERR).

25.9.1.28 IRQSET Register (Offset = 78h) [Reset = 00000000h]

IRQSET is shown in #I2S_I2S_MAP1_I2S_ALL_IRQSET_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_IRQSET_TABLE.

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Interrupt Set Register

Figure 25-39 IRQSET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED AIF_DMA_IN AIF_DMA_OUT WCLK_TIMEOUT BUS_ERR WCLK_ERR PTR_ERR
R-0h W-0h W-0h W-0h W-0h W-0h W-0h
Table 25-31 IRQSET Register Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h Reserved
5 AIF_DMA_IN W 0h 1: Sets the interrupt of IRQFLAGS.AIF_DMA_IN (unless a auto clear criteria was given at the same time, in which the set will be ignored)
4 AIF_DMA_OUT W 0h 1: Sets the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a auto clear criteria was given at the same time, in which the set will be ignored)
3 WCLK_TIMEOUT W 0h 1: Sets the interrupt of IRQFLAGS.WCLK_TIMEOUT
2 BUS_ERR W 0h 1: Sets the interrupt of IRQFLAGS.BUS_ERR
1 WCLK_ERR W 0h 1: Sets the interrupt of IRQFLAGS.WCLK_ERR
0 PTR_ERR W 0h 1: Sets the interrupt of IRQFLAGS.PTR_ERR

25.9.1.29 IRQCLR Register (Offset = 7Ch) [Reset = 00000000h]

IRQCLR is shown in #I2S_I2S_MAP1_I2S_ALL_IRQCLR_FIGURE and described in #I2S_I2S_MAP1_I2S_ALL_IRQCLR_TABLE.

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Interrupt Clear Register

Figure 25-40 IRQCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED AIF_DMA_IN AIF_DMA_OUT WCLK_TIMEOUT BUS_ERR WCLK_ERR PTR_ERR
R-0h W-0h W-0h W-0h W-0h W-0h W-0h
Table 25-32 IRQCLR Register Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h Reserved
5 AIF_DMA_IN W 0h 1: Clears the interrupt of IRQFLAGS.AIF_DMA_IN (unless a set criteria was given at the same time in which the clear will be ignored)
4 AIF_DMA_OUT W 0h 1: Clears the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a set criteria was given at the same time in which the clear will be ignored)
3 WCLK_TIMEOUT W 0h 1: Clears the interrupt of IRQFLAGS.WCLK_TIMEOUT (unless a set criteria was given at the same time in which the clear will be ignored)
2 BUS_ERR W 0h 1: Clears the interrupt of IRQFLAGS.BUS_ERR (unless a set criteria was given at the same time in which the clear will be ignored)
1 WCLK_ERR W 0h 1: Clears the interrupt of IRQFLAGS.WCLK_ERR (unless a set criteria was given at the same time in which the clear will be ignored)
0 PTR_ERR W 0h 1: Clears the interrupt of IRQFLAGS.PTR_ERR (unless a set criteria was given at the same time in which the clear will be ignored)