SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
#CPU_DWT_CPU_DWT_MAP1_TABLE_1 lists the memory-mapped registers for the CPU_DWT registers. All register offset addresses not listed in #CPU_DWT_CPU_DWT_MAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
Complex bit access types are encoded to fit into small table cells. #CPU_DWT_CPU_DWT_MAP1_LEGEND shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
CTRL is shown in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_CTRL_FIGURE and described in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_CTRL_TABLE.
Return to the Summary Table.
Control
Use the DWT Control Register to enable the DWT unit.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | NOCYCCNT | NOPRFCNT | |||||
| R/W-10h | R/W-0h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | CYCEVTENA | FOLDEVTENA | LSUEVTENA | SLEEPEVTENA | EXCEVTENA | CPIEVTENA | EXCTRCENA |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PCSAMPLEENA | SYNCTAP | CYCTAP | POSTCNT | |||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| POSTCNT | POSTPRESET | CYCCNTENA | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | 10h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 25 | NOCYCCNT | R/W | 0h | When set, CYCCNT is not supported. |
| 24 | NOPRFCNT | R/W | 0h | When set, FOLDCNT, LSUCNT, SLEEPCNT, EXCCNT, and CPICNT are not supported. |
| 23 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 22 | CYCEVTENA | R/W | 0h | Enables Cycle count event. Emits an event when the POSTCNT counter triggers it. See CYCTAP and POSTPRESET for details. This event is only emitted if PCSAMPLEENA is disabled. PCSAMPLEENA overrides the setting of this bit. 0: Cycle count events disabled 1: Cycle count events enabled |
| 21 | FOLDEVTENA | R/W | 0h | Enables Folded instruction count event. Emits an event when FOLDCNT overflows (every 256 cycles of folded instructions). A folded instruction is one that does not incur even one cycle to execute. For example, an IT instruction is folded away and so does not use up one cycle. 0: Folded instruction count events disabled. 1: Folded instruction count events enabled. |
| 20 | LSUEVTENA | R/W | 0h | Enables LSU count event. Emits an event when LSUCNT overflows (every 256 cycles of LSU operation). LSU counts include all LSU costs after the initial cycle for the instruction. 0: LSU count events disabled. 1: LSU count events enabled. |
| 19 | SLEEPEVTENA | R/W | 0h | Enables Sleep count event. Emits an event when SLEEPCNT overflows (every 256 cycles that the processor is sleeping). 0: Sleep count events disabled. 1: Sleep count events enabled. |
| 18 | EXCEVTENA | R/W | 0h | Enables Interrupt overhead event. Emits an event when EXCCNT overflows (every 256 cycles of interrupt overhead). 0x0: Interrupt overhead event disabled. 0x1: Interrupt overhead event enabled. |
| 17 | CPIEVTENA | R/W | 0h | Enables CPI count event. Emits an event when CPICNT overflows (every 256 cycles of multi-cycle instructions). 0: CPI counter events disabled. 1: CPI counter events enabled. |
| 16 | EXCTRCENA | R/W | 0h | Enables Interrupt event tracing. 0: Interrupt event trace disabled. 1: Interrupt event trace enabled. |
| 15-13 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 12 | PCSAMPLEENA | R/W | 0h | Enables PC Sampling event. A PC sample event is emitted when the POSTCNT counter triggers it. See CYCTAP and POSTPRESET for details. Enabling this bit overrides CYCEVTENA. 0: PC Sampling event disabled. 1: Sampling event enabled. |
| 11-10 | SYNCTAP | R/W | 0h | Selects a synchronization packet rate. CYCCNTENA and CPU_ITM:TCR.SYNCENA must also be enabled for this feature. Synchronization packets (if enabled) are generated on tap transitions (0 to1 or 1 to 0). 0h = Disabled. No synchronization packets 1h = Tap at bit 24 of CYCCNT 2h = Tap at bit 26 of CYCCNT 3h = Tap at bit 28 of CYCCNT |
| 9 | CYCTAP | R/W | 0h | Selects a tap on CYCCNT. These are spaced at bits [6] and [10]. When the selected bit in CYCCNT changes from 0 to 1 or 1 to 0, it emits into the POSTCNT, post-scalar counter. That counter then counts down. On a bit change when post-scalar is 0, it triggers an event for PC sampling or cycle count event (see details in CYCEVTENA).
0h = Selects bit [6] to tap 1h = Selects bit [10] to tap |
| 8-5 | POSTCNT | R/W | 0h | Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0 to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it triggers an event for PCSAMPLEENA or CYCEVTENA use. It also reloads with the value from POSTPRESET. |
| 4-1 | POSTPRESET | R/W | 0h | Reload value for post-scalar counter POSTCNT. When 0, events are triggered on each tap change (a power of 2). If this field has a non-0 value, it forms a count-down value, to be reloaded into POSTCNT each time it reaches 0. For example, a value 1 in this register means an event is formed every other tap change. |
| 0 | CYCCNTENA | R/W | 0h | Enable CYCCNT, allowing it to increment and generate synchronization and count events. If NOCYCCNT = 1, this bit reads zero and ignore writes. |
CYCCNT is shown in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_CYCCNT_FIGURE and described in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_CYCCNT_TABLE.
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Current PC Sampler Cycle Count
This register is used to count the number of core cycles. This counter can measure elapsed execution time. This is a free-running counter (this counter will not advance in power modes where free-running clock to CPU stops). The counter has three functions:
1: When CTRL.PCSAMPLEENA = 1, the PC is sampled and emitted when the selected tapped bit changes value (0 to 1 or 1 to 0) and any post-scalar value counts to 0.
2: When CTRL.CYCEVTENA = 1 , (and CTRL.PCSAMPLEENA = 0), an event is emitted when the selected tapped bit changes value (0 to 1 or 1 to 0) and any post-scalar value counts to 0.
3: Applications and debuggers can use the counter to measure elapsed execution time. By subtracting a start and an end time, an application can measure time between in-core clocks (other than when Halted in debug). This is valid to 232 core clock cycles (for example, almost 89.5 seconds at 48MHz).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CYCCNT | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | CYCCNT | R/W | 0h | Current PC Sampler Cycle Counter count value. When enabled, this counter counts the number of core cycles, except when the core is halted. The cycle counter is a free running counter, counting upwards (this counter will not advance in power modes where free-running clock to CPU stops). It wraps around to 0 on overflow. The debugger must initialize this to 0 when first enabling. |
CPICNT is shown in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_CPICNT_FIGURE and described in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_CPICNT_TABLE.
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CPI Count
This register is used to count the total number of instruction cycles beyond the first cycle.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CPICNT | ||||||||||||||||||||||||||||||
| R/W-0h | R/W-X | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 7-0 | CPICNT | R/W | X | Current CPI counter value. Increments on the additional cycles (the first cycle is not counted) required to execute all instructions except those recorded by LSUCNT. This counter also increments on all instruction fetch stalls. If CTRL.CPIEVTENA is set, an event is emitted when the counter overflows. This counter initializes to 0 when it is enabled using CTRL.CPIEVTENA. |
EXCCNT is shown in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_EXCCNT_FIGURE and described in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_EXCCNT_TABLE.
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Exception Overhead Count
This register is used to count the total cycles spent in interrupt processing.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | EXCCNT | ||||||||||||||||||||||||||||||
| R/W-0h | R/W-X | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 7-0 | EXCCNT | R/W | X | Current interrupt overhead counter value. Counts the total cycles spent in interrupt processing (for example entry stacking, return unstacking, pre-emption). An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when it is enabled using CTRL.EXCEVTENA. |
SLEEPCNT is shown in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_SLEEPCNT_FIGURE and described in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_SLEEPCNT_TABLE.
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Sleep Count
This register is used to count the total number of cycles during which the processor is sleeping.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SLEEPCNT | ||||||||||||||||||||||||||||||
| R/W-0h | R/W-X | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 7-0 | SLEEPCNT | R/W | X | Sleep counter. Counts the number of cycles during which the processor is sleeping. An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when it is enabled using CTRL.SLEEPEVTENA. Note that the sleep counter is clocked using CPU's free-running clock. In some power modes the free-running clock to CPU is gated to minimize power consumption. This means that the sleep counter will be invalid in these power modes. |
LSUCNT is shown in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_LSUCNT_FIGURE and described in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_LSUCNT_TABLE.
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LSU Count
This register is used to count the total number of cycles during which the processor is processing an LSU operation beyond the first cycle.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LSUCNT | ||||||||||||||||||||||||||||||
| R/W-0h | R/W-X | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 7-0 | LSUCNT | R/W | X | LSU counter. This counts the total number of cycles that the processor is processing an LSU operation. The initial execution cost of the instruction is not counted. For example, an LDR that takes two cycles to complete increments this counter one cycle. Equivalently, an LDR that stalls for two cycles (i.e. takes four cycles to execute), increments this counter three times. An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when it is enabled using CTRL.LSUEVTENA. |
FOLDCNT is shown in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_FOLDCNT_FIGURE and described in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_FOLDCNT_TABLE.
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Fold Count
This register is used to count the total number of folded instructions. The counter increments on each instruction which takes 0 cycles.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | FOLDCNT | ||||||||||||||||||||||||||||||
| R/W-0h | R/W-X | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 7-0 | FOLDCNT | R/W | X | This counts the total number folded instructions. This counter initializes to 0 when it is enabled using CTRL.FOLDEVTENA. |
PCSR is shown in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_PCSR_FIGURE and described in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_PCSR_TABLE.
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Program Counter Sample
This register is used to enable coarse-grained software profiling using a debug agent, without changing the currently executing code. If the core is not in debug state, the value returned is the instruction address of a recently executed instruction. If the core is in debug state, the value returned is 0xFFFFFFFF.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EIASAMPLE | |||||||||||||||||||||||||||||||
| R-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | EIASAMPLE | R | X | Execution instruction address sample, or 0xFFFFFFFF if the core is halted. |
COMP0 is shown in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_COMP0_FIGURE and described in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_COMP0_TABLE.
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Comparator 0
This register is used to write the reference value for comparator 0.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COMP | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | COMP | R/W | X | Reference value to compare against PC or the data address as given by FUNCTION0. Comparator 0 can also compare against the value of the PC Sampler Counter (CYCCNT). |
MASK0 is shown in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_MASK0_FIGURE and described in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_MASK0_TABLE.
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Mask 0
Use the DWT Mask Registers 0 to apply a mask to data addresses when matching against COMP0.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MASK | ||||||||||||||||||||||||||||||
| R/W-0h | R/W-X | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-4 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 3-0 | MASK | R/W | X | Mask on data address when matching against COMP0. This is the size of the ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) == COMP0. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP0 is 3, this matches a word access of 0, because 3 would be within the word. |
FUNCTION0 is shown in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_FUNCTION0_FIGURE and described in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_FUNCTION0_TABLE.
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Function 0
Use the DWT Function Registers 0 to control the operation of the comparator 0. This comparator can:
1. Match against either the PC or the data address. This is controlled by CYCMATCH. This function is only available for comparator 0 (COMP0).
2. Emit data or PC couples, trigger the ETM, or generate a watchpoint depending on the operation defined by FUNCTION.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | MATCHED | ||||||
| R-0h | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CYCMATCH | RESERVED | EMITRANGE | RESERVED | FUNCTION | |||
| R/W-0h | R-0h | R/W-0h | R-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 24 | MATCHED | R/W | 0h | This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. |
| 23-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 7 | CYCMATCH | R/W | 0h | This bit is only available in comparator 0. When set, COMP0 will compare against the cycle counter (CYCCNT). |
| 6 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 5 | EMITRANGE | R/W | 0h | Emit range field. This bit permits emitting offset when range match occurs. PC sampling is not supported when emit range is enabled. This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. |
| 4 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 3-0 | FUNCTION | R/W | 0h | Function settings. 0x0: Disabled 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. 0x4: Watchpoint on PC match. 0x5: Watchpoint on read. 0x6: Watchpoint on write. 0x7: Watchpoint on read or write. 0x8: ETM trigger on PC match 0x9: ETM trigger on read 0xA: ETM trigger on write 0xB: ETM trigger on read or write 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for read transfers 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for write transfers 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for read transfers 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for write transfers Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. |
COMP1 is shown in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_COMP1_FIGURE and described in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_COMP1_TABLE.
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Comparator 1
This register is used to write the reference value for comparator 1.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COMP | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | COMP | R/W | X | Reference value to compare against PC or the data address as given by FUNCTION1. Comparator 1 can also compare data values. So this register can contain reference values for data matching. |
MASK1 is shown in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_MASK1_FIGURE and described in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_MASK1_TABLE.
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Mask 1
Use the DWT Mask Registers 1 to apply a mask to data addresses when matching against COMP1.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MASK | ||||||||||||||||||||||||||||||
| R/W-0h | R/W-X | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-4 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 3-0 | MASK | R/W | X | Mask on data address when matching against COMP1. This is the size of the ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) == COMP1. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP1 is 3, this matches a word access of 0, because 3 would be within the word. |
FUNCTION1 is shown in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_FUNCTION1_FIGURE and described in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_FUNCTION1_TABLE.
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Function 1
Use the DWT Function Registers 1 to control the operation of the comparator 1. This comparator can:
1. Perform data value comparisons if associated address comparators have performed an address match. This function is only available for comparator 1 (COMP1).
2. Emit data or PC couples, trigger the ETM, or generate a watchpoint depending on the operation defined by FUNCTION.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | MATCHED | ||||||
| R-0h | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | DATAVADDR1 | ||||||
| R-0h | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| DATAVADDR0 | DATAVSIZE | LNK1ENA | DATAVMATCH | ||||
| R/W-0h | R/W-0h | R-1h | R/W-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | EMITRANGE | RESERVED | FUNCTION | ||||
| R-0h | R/W-0h | R-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 24 | MATCHED | R/W | 0h | This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. |
| 23-20 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 19-16 | DATAVADDR1 | R/W | 0h | Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1. |
| 15-12 | DATAVADDR0 | R/W | 0h | Identity of a linked address comparator for data value matching when DATAVMATCH == 1. |
| 11-10 | DATAVSIZE | R/W | 0h | Defines the size of the data in the COMP1 register that is to be matched: 0x0: Byte 0x1: Halfword 0x2: Word 0x3: Unpredictable. |
| 9 | LNK1ENA | R | 1h | Read only bit-field only supported in comparator 1. 0: DATAVADDR1 not supported 1: DATAVADDR1 supported (enabled) |
| 8 | DATAVMATCH | R/W | 0h | Data match feature: 0: Perform address comparison 1: Perform data value compare. The comparators given by DATAVADDR0 and DATAVADDR1 provide the address for the data comparison. The FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison. This bit is only available in comparator 1. |
| 7-6 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 5 | EMITRANGE | R/W | 0h | Emit range field. This bit permits emitting offset when range match occurs. PC sampling is not supported when emit range is enabled. This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. |
| 4 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 3-0 | FUNCTION | R/W | 0h | Function settings: 0x0: Disabled 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. 0x4: Watchpoint on PC match. 0x5: Watchpoint on read. 0x6: Watchpoint on write. 0x7: Watchpoint on read or write. 0x8: ETM trigger on PC match 0x9: ETM trigger on read 0xA: ETM trigger on write 0xB: ETM trigger on read or write 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for read transfers 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for write transfers 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for read transfers 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for write transfers Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: FUNCTION is overridden for comparators given by DATAVADDR0 and DATAVADDR1 if DATAVMATCH is also set. The comparators given by DATAVADDR0 and DATAVADDR1 can then only perform address comparator matches for comparator 1 data matches. Note 4: If the data matching functionality is not included during implementation it is not possible to set DATAVADDR0, DATAVADDR1, or DATAVMATCH. This means that the data matching functionality is not available in the implementation. Test the availability of data matching by writing and reading DATAVMATCH. If it is not settable then data matching is unavailable. Note 5: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. |
COMP2 is shown in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_COMP2_FIGURE and described in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_COMP2_TABLE.
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Comparator 2
This register is used to write the reference value for comparator 2.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COMP | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | COMP | R/W | X | Reference value to compare against PC or the data address as given by FUNCTION2. |
MASK2 is shown in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_MASK2_FIGURE and described in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_MASK2_TABLE.
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Mask 2
Use the DWT Mask Registers 2 to apply a mask to data addresses when matching against COMP2.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MASK | ||||||||||||||||||||||||||||||
| R/W-0h | R/W-X | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-4 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 3-0 | MASK | R/W | X | Mask on data address when matching against COMP2. This is the size of the ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) == COMP2. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP2 is 3, this matches a word access of 0, because 3 would be within the word. |
FUNCTION2 is shown in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_FUNCTION2_FIGURE and described in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_FUNCTION2_TABLE.
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Function 2
Use the DWT Function Registers 2 to control the operation of the comparator 2. This comparator can emit data or PC couples, trigger the ETM, or generate a watchpoint depending on the operation defined by FUNCTION.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | MATCHED | ||||||
| R/W-0h | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | EMITRANGE | RESERVED | FUNCTION | ||||
| R-0h | R/W-0h | R-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 24 | MATCHED | R/W | 0h | This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. |
| 23-6 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 5 | EMITRANGE | R/W | 0h | Emit range field. This bit permits emitting offset when range match occurs. PC sampling is not supported when emit range is enabled. This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. |
| 4 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 3-0 | FUNCTION | R/W | 0h | Function settings. 0x0: Disabled 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. 0x4: Watchpoint on PC match. 0x5: Watchpoint on read. 0x6: Watchpoint on write. 0x7: Watchpoint on read or write. 0x8: ETM trigger on PC match 0x9: ETM trigger on read 0xA: ETM trigger on write 0xB: ETM trigger on read or write 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for read transfers 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for write transfers 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for read transfers 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for write transfers Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. |
COMP3 is shown in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_COMP3_FIGURE and described in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_COMP3_TABLE.
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Comparator 3
This register is used to write the reference value for comparator 3.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COMP | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | COMP | R/W | X | Reference value to compare against PC or the data address as given by FUNCTION3. |
MASK3 is shown in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_MASK3_FIGURE and described in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_MASK3_TABLE.
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Mask 3
Use the DWT Mask Registers 3 to apply a mask to data addresses when matching against COMP3.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MASK | ||||||||||||||||||||||||||||||
| R/W-0h | R/W-X | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-4 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 3-0 | MASK | R/W | X | Mask on data address when matching against COMP3. This is the size of the ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) == COMP3. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP3 is 3, this matches a word access of 0, because 3 would be within the word. |
FUNCTION3 is shown in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_FUNCTION3_FIGURE and described in #CPU_DWT_CPU_DWT_MAP1_CPU_DWT_ALL_FUNCTION3_TABLE.
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Function 3
Use the DWT Function Registers 3 to control the operation of the comparator 3. This comparator can emit data or PC couples, trigger the ETM, or generate a watchpoint depending on the operation defined by FUNCTION.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | MATCHED | ||||||
| R/W-0h | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | EMITRANGE | RESERVED | FUNCTION | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 24 | MATCHED | R/W | 0h | This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. |
| 23-6 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 5 | EMITRANGE | R/W | 0h | Emit range field. This bit permits emitting offset when range match occurs. PC sampling is not supported when emit range is enabled. This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. |
| 4 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 3-0 | FUNCTION | R/W | 0h | Function settings. 0x0: Disabled 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. 0x4: Watchpoint on PC match. 0x5: Watchpoint on read. 0x6: Watchpoint on write. 0x7: Watchpoint on read or write. 0x8: ETM trigger on PC match 0x9: ETM trigger on read 0xA: ETM trigger on write 0xB: ETM trigger on read or write 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for read transfers 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for write transfers 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for read transfers 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for write transfers Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. |