SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The following software example in pseudocode describes the actions that are typically executed by the host software. The example starts the Hash engine with a new Hash session that receives the input data through the DMA interface. In the end, the intermediate digest (nonfinal Hash operation) or the finalized Hash digest (final Hash operation) is read as a result digest through the slave interface.
// configure master control module
write CTRL_ALG_SEL 0x0000_0008 // enable DMA path to the SHA-2 engine
write CTRL_INT_CLR 0x0000_0001 // clear any outstanding events
// configure hash engine
write HASH_MODE = 0x0000_0021 // indicate the start of a new hash session and SHA512
write HASH_LENGTH_L// write the length of the message (lo)
write HASH_LENGTH_H// write the length of the message (hi)
// if the final digest is required (pad the input DMA data), write the following register
write HASH_IO_BUF_CTRL = 0x80 // pad the data that is transferred via DMA
// configure DMAC
write DMAC_CH0_CTRL 0x0000_00001 // enable DMA channel 0 for message data
write DMAC_CH0_EXTADDR <ext_memory_address> // base address of the data in ext. memory
write DMAC_CH0_DMALENGTH <length> // input data in bytes, equal to
// the message length
wait CTRL_INT_STAT[0] = '1' // wait for operation done (hash and DMAC are ready)
check CTRL_INT_STAT[31] == '0' // check for the absence of errors
// read digest
read HASH_DIGEST_A
...
read HASH_DIGEST_P
// acknowledge result and clear interrupts
write HASH_IO_BUF_CTRL = 0x0000_0001// acknowledge reading of the digest
write CTRL_INT_CLR 0x0000_0001// clear the interrupt
write CTRL_ALG_SEL 0x0000_0000// disable the master control/DMA clock
// end of algorithm