SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
Table 13-46 provides mapping of the internal registers of the PKA engine, including PKA and TRNG engines, to the external address bus.
TRNG is not part of the PKA engine used for the CC13x2x7 and CC26x2x7 device platform.
The register spaces are selectable using bits [15:14] of the address bus.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Masked for PLB configuration and skipped for AGB configuration | Register space selection | Submodule address (32-bit aligned) | |||||||||||||||||||||||||||||
| EIP-150 internal registers and AIC registers | |||||||||||||||||||||||||||||||
| – | – | – | – | – | – | – | – | – | – | – | – | – | – | – | – | 1 | 0 | A | A | A | A | A | A | A | A | A | A | A | A | 0 | 0 |
| PKA Engine | |||||||||||||||||||||||||||||||
| – | – | – | – | – | – | – | – | – | – | – | – | – | – | – | – | 0 | 1 | 0 | A | A | A | A | A | A | A | A | A | A | A | 0 | 0 |
| PKA RAM (Program RAM) | |||||||||||||||||||||||||||||||
| – | – | – | – | – | – | – | – | – | – | – | – | – | – | – | – | 0 | 1 | 1 | A | A | A | A | A | A | A | A | A | A | A | 0 | 0 |
| TRNG Engine | |||||||||||||||||||||||||||||||
| – | – | – | – | – | – | – | – | – | – | – | – | – | – | – | – | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | A | A | A | A | A | 0 | 0 |
The complete set of control registers enables access to PKCP and sequencer control/status registers. Of these registers, only the PKCP control registers, one sequencer control and status register, and a hardware and firmware revision register are listed in Table 13-47.
| 6-Bit Word Offset | Name | Access | Size (Bits) | Reset Value | Description |
|---|---|---|---|---|---|
| 0x00 | PKA_APTR | R/W | 11 | 000h | A operand address offset |
| 0x01 | PKA_BPTR | R/W | 11 | 000h | B operand address offset |
| 0x02 | PKA_CPTR | R/W | 11 | 000h | C operand and result address offset |
| 0x03 | PKA_DPTR | R/W | 11 | 000h | D operand and result address offset |
| 0x04 | PKA_ALENGTH | R/W | 9 | 000h | Length of A operand |
| 0x05 | PKA_BLENGTH | R/W | 9 | 000h | Length of B operand |
| 0x06 | PKA_SHIFT | R/W | 5 | 00h | Bits to shift |
| 0x07 | PKA_FUNCTION | R/W | 15 + 1 + 1 | 0000h 0b 0b | Function code, run control and status, and stall result control |
| 0x08 | PKA_COMPARE | R | 3 | 001b | Result of compare |
| 0x09 | PKA_MSW | R | 11 + 1 | 000h 1b | MS nonzero word address |
| 0x0A | PKA_DIVMSW | R | 11 + 1 | 000h 1b | MS nonzero word address for remainder (MOD and DIV operations) |
| 0x32 | PKA_SEQ_CTRL | R/W | 8 + 8 + 1 | 00h 00h | Sequencer control, status, and reset |
| 0x3D | PKA_OPTIONS | R | 32 | – | Hardware configured options |
| 0x3E | PKA_SW_REV | R | 16 | 0000h | Firmware revision numbers and capabilities |
| 0x3F | PKA_REVISION | R | 28 | – | Hardware revision numbers and EIP code |