SWCU192 User guide | 德州仪器 TI.com.cn

SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

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11. 993
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997

8.8.1 OSC_DIG Registers

#OSC_DIG_OSC_DIG_MAP1_TABLE_1 lists the memory-mapped registers for the OSC_DIG registers. All register offset addresses not listed in #OSC_DIG_OSC_DIG_MAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 8-8 OSC_DIG Registers

Offset	Acronym	Register Name	Section
0h	CTL0	Control 0	#OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_CTL0
4h	CTL1	Control 1	#OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_CTL1
8h	RADCEXTCFG	RADC External Configuration	#OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_RADCEXTCFG
Ch	AMPCOMPCTL	Amplitude Compensation Control	#OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_AMPCOMPCTL
10h	AMPCOMPTH1	Amplitude Compensation Threshold 1	#OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_AMPCOMPTH1
14h	AMPCOMPTH2	Amplitude Compensation Threshold 2	#OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_AMPCOMPTH2
18h	ANABYPASSVAL1	Analog Bypass Values 1	#OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_ANABYPASSVAL1
1Ch	ANABYPASSVAL2	Internal	#OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_ANABYPASSVAL2
20h	ATESTCTL	Analog Test Control	#OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_ATESTCTL
24h	ADCDOUBLERNANOAMPCTL	ADC Doubler Nanoamp Control	#OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_ADCDOUBLERNANOAMPCTL
28h	XOSCHFCTL	XOSCHF Control	#OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_XOSCHFCTL
2Ch	LFOSCCTL	Low Frequency Oscillator Control	#OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_LFOSCCTL
30h	RCOSCHFCTL	RCOSCHF Control	#OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_RCOSCHFCTL
34h	RCOSCMFCTL	RCOSC_MF Control	#OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_RCOSCMFCTL
3Ch	STAT0	Status 0	#OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_STAT0
40h	STAT1	Status 1	#OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_STAT1
44h	STAT2	Status 2	#OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_STAT2

Complex bit access types are encoded to fit into small table cells. #OSC_DIG_OSC_DIG_MAP1_LEGEND shows the codes that are used for access types in this section.

Table 8-9 OSC_DIG Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

8.8.1.1 CTL0 Register (Offset = 0h) [Reset = 00000000h]

CTL0 is shown in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_CTL0_FIGURE and described in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_CTL0_TABLE.

Return to the Summary Table.

Control 0
Controls clock source selects

Figure 8-7 CTL0 Register

31	30	29	28	27	26	25	24
XTAL_IS_24M	RESERVED	BYPASS_XOSC_LF_CLK_QUAL	BYPASS_RCOSC_LF_CLK_QUAL	DOUBLER_START_DURATION		DOUBLER_RESET_DURATION	CLK_DCDC_SRC_SEL
R/W-0h	R-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED	RESERVED	RESERVED	RCOSC_LF_TRIMMED	XOSC_HF_POWER_MODE	XOSC_LF_DIG_BYPASS	CLK_LOSS_EN	ACLK_TDC_SRC_SEL
R-0h	R-0h	R-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
ACLK_TDC_SRC_SEL	ACLK_REF_SRC_SEL			SCLK_LF_SRC_SEL		RESERVED	SCLK_HF_SRC_SEL
R/W-0h	R/W-0h			R/W-0h		R-0h	R/W-0h

Table 8-10 CTL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	XTAL_IS_24M	R/W	0h	Set based on the accurate high frequency XTAL.
30	RESERVED	R	0h	Reserved
29	BYPASS_XOSC_LF_CLK_QUAL	R/W	0h	Internal. Only to be used through TI provided API.
28	BYPASS_RCOSC_LF_CLK_QUAL	R/W	0h	Internal. Only to be used through TI provided API.
27-26	DOUBLER_START_DURATION	R/W	0h	Internal. Only to be used through TI provided API.
25	DOUBLER_RESET_DURATION	R/W	0h	Internal. Only to be used through TI provided API.
24	CLK_DCDC_SRC_SEL	R/W	0h	Select DCDC clock source. 0: CLK_DCDC is 48 MHz clock from RCOSC or XOSC 1: CLK_DCDC is always 48 MHz clock from RCOSC
23-15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RCOSC_LF_TRIMMED	R/W	0h	Internal. Only to be used through TI provided API.
11	XOSC_HF_POWER_MODE	R/W	0h	Internal. Only to be used through TI provided API.
10	XOSC_LF_DIG_BYPASS	R/W	0h	Bypass XOSC_LF and use the digital input clock from AON for the xosc_lf clock. 0: Use 32kHz XOSC as xosc_lf clock source 1: Use digital input (from AON) as xosc_lf clock source. This bit will only have effect when SCLK_LF_SRC_SEL is selecting the xosc_lf as the sclk_lf source. The muxing performed by this bit is not glitch free. The following procedure must be followed when changing this field to avoid glitches on sclk_lf. 1) Set SCLK_LF_SRC_SEL to select any source other than the xosc_lf clock source. 2) Set or clear this bit to bypass or not bypass the xosc_lf. 3) Set SCLK_LF_SRC_SEL to use xosc_lf. It is recommended that either the rcosc_hf or xosc_hf (whichever is currently active) be selected as the source in step 1 above. This provides a faster clock change.
9	CLK_LOSS_EN	R/W	0h	Enable clock loss detection and hence the indicators to the system controller. Checks both SCLK_HF, SCLK_MF and SCLK_LF clock loss indicators. 0: Disable 1: Enable Clock loss detection must be disabled when changing the sclk_lf source. STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf source has completed.
8-7	ACLK_TDC_SRC_SEL	R/W	0h	Source select for aclk_tdc. 00: RCOSC_HF (48MHz) 01: RCOSC_HF (24MHz) 10: XOSC_HF (24MHz) 11: Not used
6-4	ACLK_REF_SRC_SEL	R/W	0h	Source select for aclk_ref 000: RCOSC_HF derived (31.25kHz) 001: XOSC_HF derived (31.25kHz) 010: RCOSC_LF (32kHz) 011: XOSC_LF (32.768kHz) 100: RCOSC_MF (2MHz) 101-111: Not used
3-2	SCLK_LF_SRC_SEL	R/W	0h	Source select for sclk_lf 0h = Low frequency clock derived from High Frequency RCOSC 1h = Low frequency clock derived from High Frequency XOSC 2h = Low frequency RCOSC 3h = Low frequency XOSC
1	RESERVED	R	0h	Reserved
0	SCLK_HF_SRC_SEL	R/W	0h	Source select for sclk_hf. 0h = High frequency RCOSC clock 1h = High frequency XOSC

8.8.1.2 CTL1 Register (Offset = 4h) [Reset = 00000000h]

CTL1 is shown in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_CTL1_FIGURE and described in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_CTL1_TABLE.

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Control 1
This register contains OSC_DIG configuration

Figure 8-8 CTL1 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED	RCOSCHFCTRIMFRACT					RCOSCHFCTRIMFRACT_EN	RESERVED
R-0h	R/W-0h					R/W-0h	R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						XOSC_HF_FAST_START
R-0h						R/W-0h

Table 8-11 CTL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R	0h	Reserved
22-18	RCOSCHFCTRIMFRACT	R/W	0h	Internal. Only to be used through TI provided API.
17	RCOSCHFCTRIMFRACT_EN	R/W	0h	Internal. Only to be used through TI provided API.
16-2	RESERVED	R	0h	Reserved
1-0	XOSC_HF_FAST_START	R/W	0h	Internal. Only to be used through TI provided API.

8.8.1.3 RADCEXTCFG Register (Offset = 8h) [Reset = 00000000h]

RADCEXTCFG is shown in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_RADCEXTCFG_FIGURE and described in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_RADCEXTCFG_TABLE.

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RADC External Configuration

Figure 8-9 RADCEXTCFG Register

31	30	29	28	27	26	25	24
HPM_IBIAS_WAIT_CNT
R/W-0h

23	22	21	20	19	18	17	16
HPM_IBIAS_WAIT_CNT		LPM_IBIAS_WAIT_CNT
R/W-0h		R/W-0h

15	14	13	12	11	10	9	8
IDAC_STEP				RADC_DAC_TH
R/W-0h				R/W-0h

7	6	5	4	3	2	1	0
RADC_DAC_TH		RADC_MODE_IS_SAR	RESERVED
R/W-0h		R/W-0h	R-0h

Table 8-12 RADCEXTCFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-22	HPM_IBIAS_WAIT_CNT	R/W	0h	Internal. Only to be used through TI provided API.
21-16	LPM_IBIAS_WAIT_CNT	R/W	0h	Internal. Only to be used through TI provided API.
15-12	IDAC_STEP	R/W	0h	Internal. Only to be used through TI provided API.
11-6	RADC_DAC_TH	R/W	0h	Internal. Only to be used through TI provided API.
5	RADC_MODE_IS_SAR	R/W	0h	Internal. Only to be used through TI provided API.
4-0	RESERVED	R	0h	Reserved

8.8.1.4 AMPCOMPCTL Register (Offset = Ch) [Reset = 00000000h]

AMPCOMPCTL is shown in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_AMPCOMPCTL_FIGURE and described in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_AMPCOMPCTL_TABLE.

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Amplitude Compensation Control

Figure 8-10 AMPCOMPCTL Register

31	30	29	28	27	26	25	24
RESERVED	AMPCOMP_REQ_MODE	AMPCOMP_FSM_UPDATE_RATE		AMPCOMP_SW_CTRL	AMPCOMP_SW_EN	RESERVED
R-0h	R/W-0h	R/W-0h		R/W-0h	R/W-0h	R-0h

23	22	21	20	19	18	17	16
IBIAS_OFFSET				IBIAS_INIT
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
LPM_IBIAS_WAIT_CNT_FINAL
R/W-0h

7	6	5	4	3	2	1	0
CAP_STEP				IBIASCAP_HPTOLP_OL_CNT
R/W-0h				R/W-0h

Table 8-13 AMPCOMPCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	AMPCOMP_REQ_MODE	R/W	0h	Internal. Only to be used through TI provided API.
29-28	AMPCOMP_FSM_UPDATE_RATE	R/W	0h	Internal. Only to be used through TI provided API.
27	AMPCOMP_SW_CTRL	R/W	0h	Internal. Only to be used through TI provided API.
26	AMPCOMP_SW_EN	R/W	0h	Internal. Only to be used through TI provided API.
25-24	RESERVED	R	0h	Reserved
23-20	IBIAS_OFFSET	R/W	0h	Internal. Only to be used through TI provided API.
19-16	IBIAS_INIT	R/W	0h	Internal. Only to be used through TI provided API.
15-8	LPM_IBIAS_WAIT_CNT_FINAL	R/W	0h	Internal. Only to be used through TI provided API.
7-4	CAP_STEP	R/W	0h	Internal. Only to be used through TI provided API.
3-0	IBIASCAP_HPTOLP_OL_CNT	R/W	0h	Internal. Only to be used through TI provided API.

8.8.1.5 AMPCOMPTH1 Register (Offset = 10h) [Reset = 00000000h]

AMPCOMPTH1 is shown in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_AMPCOMPTH1_FIGURE and described in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_AMPCOMPTH1_TABLE.

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Amplitude Compensation Threshold 1
This register contains threshold values for amplitude compensation algorithm

Figure 8-11 AMPCOMPTH1 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
HPMRAMP3_LTH						RESERVED
R/W-0h						R-0h

15	14	13	12	11	10	9	8
HPMRAMP3_HTH						IBIASCAP_LPTOHP_OL_CNT
R/W-0h						R/W-0h

7	6	5	4	3	2	1	0
IBIASCAP_LPTOHP_OL_CNT		HPMRAMP1_TH
R/W-0h		R/W-0h

Table 8-14 AMPCOMPTH1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-18	HPMRAMP3_LTH	R/W	0h	Internal. Only to be used through TI provided API.
17-16	RESERVED	R	0h	Reserved
15-10	HPMRAMP3_HTH	R/W	0h	Internal. Only to be used through TI provided API.
9-6	IBIASCAP_LPTOHP_OL_CNT	R/W	0h	Internal. Only to be used through TI provided API.
5-0	HPMRAMP1_TH	R/W	0h	Internal. Only to be used through TI provided API.

8.8.1.6 AMPCOMPTH2 Register (Offset = 14h) [Reset = 00000000h]

AMPCOMPTH2 is shown in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_AMPCOMPTH2_FIGURE and described in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_AMPCOMPTH2_TABLE.

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Amplitude Compensation Threshold 2
This register contains threshold values for amplitude compensation algorithm.

Figure 8-12 AMPCOMPTH2 Register

31	30	29	28	27	26	25	24
LPMUPDATE_LTH						RESERVED
R/W-0h						R-0h

23	22	21	20	19	18	17	16
LPMUPDATE_HTH						RESERVED
R/W-0h						R-0h

15	14	13	12	11	10	9	8
ADC_COMP_AMPTH_LPM						RESERVED
R/W-0h						R-0h

7	6	5	4	3	2	1	0
ADC_COMP_AMPTH_HPM						RESERVED
R/W-0h						R-0h

Table 8-15 AMPCOMPTH2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	LPMUPDATE_LTH	R/W	0h	Internal. Only to be used through TI provided API.
25-24	RESERVED	R	0h	Reserved
23-18	LPMUPDATE_HTH	R/W	0h	Internal. Only to be used through TI provided API.
17-16	RESERVED	R	0h	Reserved
15-10	ADC_COMP_AMPTH_LPM	R/W	0h	Internal. Only to be used through TI provided API.
9-8	RESERVED	R	0h	Reserved
7-2	ADC_COMP_AMPTH_HPM	R/W	0h	Internal. Only to be used through TI provided API.
1-0	RESERVED	R	0h	Reserved

8.8.1.7 ANABYPASSVAL1 Register (Offset = 18h) [Reset = 00000000h]

ANABYPASSVAL1 is shown in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_ANABYPASSVAL1_FIGURE and described in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_ANABYPASSVAL1_TABLE.

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Analog Bypass Values 1

Figure 8-13 ANABYPASSVAL1 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED				XOSC_HF_ROW_Q12
R-0h				R/W-0h

15	14	13	12	11	10	9	8
XOSC_HF_COLUMN_Q12
R/W-0h

7	6	5	4	3	2	1	0
XOSC_HF_COLUMN_Q12
R/W-0h

Table 8-16 ANABYPASSVAL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19-16	XOSC_HF_ROW_Q12	R/W	0h	Internal. Only to be used through TI provided API.
15-0	XOSC_HF_COLUMN_Q12	R/W	0h	Internal. Only to be used through TI provided API.

8.8.1.8 ANABYPASSVAL2 Register (Offset = 1Ch) [Reset = 00000000h]

ANABYPASSVAL2 is shown in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_ANABYPASSVAL2_FIGURE and described in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_ANABYPASSVAL2_TABLE.

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Internal. Only to be used through TI provided API.

Figure 8-14 ANABYPASSVAL2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED		XOSC_HF_IBIASTHERM
R-0h		R/W-0h

Table 8-17 ANABYPASSVAL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-14	RESERVED	R	0h	Reserved
13-0	XOSC_HF_IBIASTHERM	R/W	0h	Internal. Only to be used through TI provided API.

8.8.1.9 ATESTCTL Register (Offset = 20h) [Reset = 00000000h]

ATESTCTL is shown in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_ATESTCTL_FIGURE and described in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_ATESTCTL_TABLE.

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Analog Test Control

Figure 8-15 ATESTCTL Register

31	30	29	28	27	26	25	24
SCLK_LF_AUX_EN	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
TEST_RCOSCMF		ATEST_RCOSCMF		RESERVED
R/W-0h		R/W-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 8-18 ATESTCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	SCLK_LF_AUX_EN	R/W	0h	Enable 32 kHz clock to AUX_COMPB.
30-16	RESERVED	R	0h	Reserved
15-14	TEST_RCOSCMF	R/W	0h	Test mode control for RCOSC_MF 0x0: test modes disabled 0x1: boosted bias current into self biased inverter 0x2: clock qualification disabled 0x3: boosted bias current into self biased inverter + clock qualification disabled
13-12	ATEST_RCOSCMF	R/W	0h	ATEST control for RCOSC_MF 0x0: ATEST disabled 0x1: ATEST enabled, VDD_LOCAL connected, ATEST internal to *RCOSC_MF enabled to send out 2MHz clock. 0x2: ATEST disabled 0x3: ATEST enabled, bias current connected, ATEST internal to *RCOSC_MF enabled to send out 2MHz clock.
11-0	RESERVED	R	0h	Reserved

8.8.1.10 ADCDOUBLERNANOAMPCTL Register (Offset = 24h) [Reset = 00000000h]

ADCDOUBLERNANOAMPCTL is shown in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_ADCDOUBLERNANOAMPCTL_FIGURE and described in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_ADCDOUBLERNANOAMPCTL_TABLE.

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ADC Doubler Nanoamp Control

Figure 8-16 ADCDOUBLERNANOAMPCTL Register

31	30	29	28	27	26	25	24
RESERVED							NANOAMP_BIAS_ENABLE
R-0h							R/W-0h

23	22	21	20	19	18	17	16
SPARE23	RESERVED
R/W-0h	R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED		ADC_SH_MODE_EN	ADC_SH_VBUF_EN	RESERVED		ADC_IREF_CTRL
R-0h		R/W-0h	R/W-0h	R-0h		R/W-0h

Table 8-19 ADCDOUBLERNANOAMPCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24	NANOAMP_BIAS_ENABLE	R/W	0h	Internal. Only to be used through TI provided API.
23	SPARE23	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
22-6	RESERVED	R	0h	Reserved
5	ADC_SH_MODE_EN	R/W	0h	Internal. Only to be used through TI provided API.
4	ADC_SH_VBUF_EN	R/W	0h	Internal. Only to be used through TI provided API.
3-2	RESERVED	R	0h	Reserved
1-0	ADC_IREF_CTRL	R/W	0h	Internal. Only to be used through TI provided API.

8.8.1.11 XOSCHFCTL Register (Offset = 28h) [Reset = 00000000h]

XOSCHFCTL is shown in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_XOSCHFCTL_FIGURE and described in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_XOSCHFCTL_TABLE.

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XOSCHF Control

Figure 8-17 XOSCHFCTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED		TCXO_MODE_XOSC_HF_EN	TCXO_MODE	RESERVED		PEAK_DET_ITRIM
R-0h		R/W-0h	R/W-0h	R-0h		R/W-0h

7	6	5	4	3	2	1	0
RESERVED	BYPASS	RESERVED	HP_BUF_ITRIM			LP_BUF_ITRIM
R-0h	R/W-0h	R-0h	R/W-0h			R/W-0h

Table 8-20 XOSCHFCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-14	RESERVED	R	0h	Reserved
13	TCXO_MODE_XOSC_HF_EN	R/W	0h	If this register is 1 when TCXO_MODE is 1, then the XOSC_HF is enabled, turning on the XOSC_HF bias current allowing a DC bias point to be provided to the clipped-sine wave clock signal on external input.
12	TCXO_MODE	R/W	0h	If this register is 1 when BYPASS is 1, this will enable clock qualification on the TCXO clock on external input. This register has no effect when BYPASS is 0.
11-10	RESERVED	R	0h	Reserved
9-8	PEAK_DET_ITRIM	R/W	0h	Internal. Only to be used through TI provided API.
7	RESERVED	R	0h	Reserved
6	BYPASS	R/W	0h	Internal. Only to be used through TI provided API.
5	RESERVED	R	0h	Reserved
4-2	HP_BUF_ITRIM	R/W	0h	Internal. Only to be used through TI provided API.
1-0	LP_BUF_ITRIM	R/W	0h	Internal. Only to be used through TI provided API.

8.8.1.12 LFOSCCTL Register (Offset = 2Ch) [Reset = 00000000h]

LFOSCCTL is shown in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_LFOSCCTL_FIGURE and described in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_LFOSCCTL_TABLE.

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Low Frequency Oscillator Control

Figure 8-18 LFOSCCTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
XOSCLF_REGULATOR_TRIM		XOSCLF_CMIRRWR_RATIO				RESERVED
R/W-0h		R/W-0h				R-0h

15	14	13	12	11	10	9	8
RESERVED						RCOSCLF_RTUNE_TRIM
R-0h						R/W-0h

7	6	5	4	3	2	1	0
RCOSCLF_CTUNE_TRIM
R/W-0h

Table 8-21 LFOSCCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-22	XOSCLF_REGULATOR_TRIM	R/W	0h	Internal. Only to be used through TI provided API.
21-18	XOSCLF_CMIRRWR_RATIO	R/W	0h	Internal. Only to be used through TI provided API.
17-10	RESERVED	R	0h	Reserved
9-8	RCOSCLF_RTUNE_TRIM	R/W	0h	Internal. Only to be used through TI provided API.
7-0	RCOSCLF_CTUNE_TRIM	R/W	0h	Internal. Only to be used through TI provided API.

8.8.1.13 RCOSCHFCTL Register (Offset = 30h) [Reset = 00000000h]

RCOSCHFCTL is shown in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_RCOSCHFCTL_FIGURE and described in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_RCOSCHFCTL_TABLE.

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RCOSCHF Control

Figure 8-19 RCOSCHFCTL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RCOSCHF_CTRIM								RESERVED
R/W-0h								R-0h

Table 8-22 RCOSCHFCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-8	RCOSCHF_CTRIM	R/W	0h	Internal. Only to be used through TI provided API.
7-0	RESERVED	R	0h	Reserved

8.8.1.14 RCOSCMFCTL Register (Offset = 34h) [Reset = 00000000h]

RCOSCMFCTL is shown in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_RCOSCMFCTL_FIGURE and described in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_RCOSCMFCTL_TABLE.

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RCOSC_MF Control

Figure 8-20 RCOSCMFCTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RCOSC_MF_CAP_ARRAY							RCOSC_MF_REG_SEL
R/W-0h							R/W-0h

7	6	5	4	3	2	1	0
RCOSC_MF_RES_COARSE		RCOSC_MF_RES_FINE		RCOSC_MF_BIAS_ADJ
R/W-0h		R/W-0h		R/W-0h

Table 8-23 RCOSCMFCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-9	RCOSC_MF_CAP_ARRAY	R/W	0h	Adjust RCOSC_MF capacitor array. 0x0: nominal frequency, 0.625pF 0x40: highest frequency, 0.125pF 0x3F: lowest frequency, 1.125pF
8	RCOSC_MF_REG_SEL	R/W	0h	Choose regulator type. 0: default 1: alternate
7-6	RCOSC_MF_RES_COARSE	R/W	0h	Select coarse resistor for frequency adjustment. 0x0: 400kΩs, default 0x1: 300kΩs, min 0x2: 600kΩs, max 0x3: 500kΩs
5-4	RCOSC_MF_RES_FINE	R/W	0h	Select fine resistor for frequency adjustment. 0x0: 11kΩs, minimum resistance, max freq 0x1: 13kΩs 0x2: 16kΩs 0x3: 20kΩs, max resistance, min freq
3-0	RCOSC_MF_BIAS_ADJ	R/W	0h	Adjusts bias current to RCOSC_MF. 0x8 minimum current 0x0 default current 0x7 maximum current

8.8.1.15 STAT0 Register (Offset = 3Ch) [Reset = 00000000h]

STAT0 is shown in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_STAT0_FIGURE and described in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_STAT0_TABLE.

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Status 0
This register contains status signals from OSC_DIG

Figure 8-21 STAT0 Register

31	30	29	28	27	26	25	24
RESERVED	SCLK_LF_SRC		SCLK_HF_SRC	RESERVED
R-0h	R-0h		R-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED	RCOSC_HF_EN	RCOSC_LF_EN	XOSC_LF_EN	CLK_DCDC_RDY	CLK_DCDC_RDY_ACK	SCLK_HF_LOSS	SCLK_LF_LOSS
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

15	14	13	12	11	10	9	8
XOSC_HF_EN	RESERVED	XB_48M_CLK_EN	RESERVED	XOSC_HF_LP_BUF_EN	XOSC_HF_HP_BUF_EN	RESERVED	ADC_THMET
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
ADC_DATA_READY	ADC_DATA						PENDINGSCLKHFSWITCHING
R-0h	R-0h						R-0h

Table 8-24 STAT0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30-29	SCLK_LF_SRC	R	0h	Indicates source for the sclk_lf 0h = Low frequency clock derived from High Frequency RCOSC 1h = Low frequency clock derived from High Frequency XOSC 2h = Low frequency RCOSC 3h = Low frequency XOSC
28	SCLK_HF_SRC	R	0h	Indicates source for the sclk_hf 0h = High frequency RCOSC clock 1h = High frequency XOSC
27-23	RESERVED	R	0h	Reserved
22	RCOSC_HF_EN	R	0h	RCOSC_HF_EN
21	RCOSC_LF_EN	R	0h	RCOSC_LF_EN
20	XOSC_LF_EN	R	0h	XOSC_LF_EN
19	CLK_DCDC_RDY	R	0h	CLK_DCDC_RDY
18	CLK_DCDC_RDY_ACK	R	0h	CLK_DCDC_RDY_ACK
17	SCLK_HF_LOSS	R	0h	Indicates sclk_hf is lost
16	SCLK_LF_LOSS	R	0h	Indicates sclk_lf is lost
15	XOSC_HF_EN	R	0h	Indicates that XOSC_HF is enabled.
14	RESERVED	R	0h	Reserved
13	XB_48M_CLK_EN	R	0h	Indicates that the 48MHz clock from the DOUBLER is enabled. It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler bypass for the 48MHz crystal).
12	RESERVED	R	0h	Reserved
11	XOSC_HF_LP_BUF_EN	R	0h	XOSC_HF_LP_BUF_EN
10	XOSC_HF_HP_BUF_EN	R	0h	XOSC_HF_HP_BUF_EN
9	RESERVED	R	0h	Reserved
8	ADC_THMET	R	0h	ADC_THMET
7	ADC_DATA_READY	R	0h	indicates when adc_data is ready.
6-1	ADC_DATA	R	0h	adc_data
0	PENDINGSCLKHFSWITCHING	R	0h	Indicates when SCLK_HF clock source is ready to be switched

8.8.1.16 STAT1 Register (Offset = 40h) [Reset = 00000000h]

STAT1 is shown in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_STAT1_FIGURE and described in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_STAT1_TABLE.

Return to the Summary Table.

Status 1
This register contains status signals from OSC_DIG

Figure 8-22 STAT1 Register

31	30	29	28	27	26	25	24
RAMPSTATE				HPM_UPDATE_AMP
R-0h				R-0h

23	22	21	20	19	18	17	16
HPM_UPDATE_AMP		LPM_UPDATE_AMP
R-0h		R-0h

15	14	13	12	11	10	9	8
FORCE_RCOSC_HF	SCLK_HF_EN	SCLK_MF_EN	ACLK_ADC_EN	ACLK_TDC_EN	ACLK_REF_EN	CLK_CHP_EN	CLK_DCDC_EN
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
SCLK_HF_GOOD	SCLK_MF_GOOD	SCLK_LF_GOOD	ACLK_ADC_GOOD	ACLK_TDC_GOOD	ACLK_REF_GOOD	CLK_CHP_GOOD	CLK_DCDC_GOOD
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 8-25 STAT1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RAMPSTATE	R	0h	AMPCOMP FSM State 0h = RESET 1h = INITIALIZATION 2h = HPM_RAMP1 3h = HPM_RAMP2 4h = HPM_RAMP3 5h = HPM_UPDATE 6h = IDAC_INCREMENT 7h = IBIAS_CAP_UPDATE 8h = IBIAS_DECREMENT_WITH_MEASURE 9h = LPM_UPDATE Ah = IBIAS_INCREMENT Bh = IDAC_DECREMENT_WITH_MEASURE Ch = DUMMY_TO_INIT_1 Dh = FAST_START Eh = FAST_START_SETTLE
27-22	HPM_UPDATE_AMP	R	0h	XOSC_HF amplitude during HPM_UPDATE state. When amplitude compensation of XOSC_HF is enabled in high performance mode, this value is the amplitude of the crystal oscillations measured by the on-chip oscillator ADC, divided by 15 mV. For example, a value of 0x20 would indicate that the amplitude of the crystal is approximately 480 mV. To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero value.
21-16	LPM_UPDATE_AMP	R	0h	XOSC_HF amplitude during LPM_UPDATE state When amplitude compensation of XOSC_HF is enabled in low power mode, this value is the amplitude of the crystal oscillations measured by the on-chip oscillator ADC, divided by 15 mV. For example, a value of 0x20 would indicate that the amplitude of the crystal is approximately 480 mV. To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero value.
15	FORCE_RCOSC_HF	R	0h	force_rcosc_hf
14	SCLK_HF_EN	R	0h	SCLK_HF_EN
13	SCLK_MF_EN	R	0h	SCLK_MF_EN
12	ACLK_ADC_EN	R	0h	ACLK_ADC_EN
11	ACLK_TDC_EN	R	0h	ACLK_TDC_EN
10	ACLK_REF_EN	R	0h	ACLK_REF_EN
9	CLK_CHP_EN	R	0h	CLK_CHP_EN
8	CLK_DCDC_EN	R	0h	CLK_DCDC_EN
7	SCLK_HF_GOOD	R	0h	SCLK_HF_GOOD
6	SCLK_MF_GOOD	R	0h	SCLK_MF_GOOD
5	SCLK_LF_GOOD	R	0h	SCLK_LF_GOOD
4	ACLK_ADC_GOOD	R	0h	ACLK_ADC_GOOD
3	ACLK_TDC_GOOD	R	0h	ACLK_TDC_GOOD
2	ACLK_REF_GOOD	R	0h	ACLK_REF_GOOD.
1	CLK_CHP_GOOD	R	0h	CLK_CHP_GOOD
0	CLK_DCDC_GOOD	R	0h	CLK_DCDC_GOOD

8.8.1.17 STAT2 Register (Offset = 44h) [Reset = 00000000h]

STAT2 is shown in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_STAT2_FIGURE and described in #OSC_DIG_OSC_DIG_MAP1_OSC_DIG_ALL_STAT2_TABLE.

Return to the Summary Table.

Status 2
This register contains status signals from AMPCOMP FSM

Figure 8-23 STAT2 Register

31	30	29	28	27	26	25	24
ADC_DCBIAS						HPM_RAMP1_THMET	HPM_RAMP2_THMET
R-0h						R-0h	R-0h

23	22	21	20	19	18	17	16
HPM_RAMP3_THMET	RESERVED
R-0h	R-0h

15	14	13	12	11	10	9	8
RAMPSTATE				RESERVED
R-0h				R-0h

7	6	5	4	3	2	1	0
RESERVED				AMPCOMP_REQ	XOSC_HF_AMPGOOD	XOSC_HF_FREQGOOD	XOSC_HF_RF_FREQGOOD
R-0h				R-0h	R-0h	R-0h	R-0h

Table 8-26 STAT2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	ADC_DCBIAS	R	0h	DC Bias read by RADC during SAR mode The value is an unsigned integer. It is used for debug only.
25	HPM_RAMP1_THMET	R	0h	Indication of threshold is met for hpm_ramp1
24	HPM_RAMP2_THMET	R	0h	Indication of threshold is met for hpm_ramp2
23	HPM_RAMP3_THMET	R	0h	Indication of threshold is met for hpm_ramp3
22-16	RESERVED	R	0h	Reserved
15-12	RAMPSTATE	R	0h	xosc_hf amplitude compensation FSM This is identical to STAT1.RAMPSTATE. See that description for encoding.
11-4	RESERVED	R	0h	Reserved
3	AMPCOMP_REQ	R	0h	ampcomp_req
2	XOSC_HF_AMPGOOD	R	0h	amplitude of xosc_hf is within the required threshold (set by DDI). Not used for anything just for debug/status
1	XOSC_HF_FREQGOOD	R	0h	frequency of xosc_hf is good to use for the digital clocks
0	XOSC_HF_RF_FREQGOOD	R	0h	frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio operations. Used for SW to start synthesizer.