SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
23.4.4.6 Motorola SPI Frame Format With SPO = 1 and SPH = 1
Figure 23-9 shows the transfer signal sequence for Motorola SPI format with SPO = 1 and SPH = 1, which covers both single and continuous transfers.
In this configuration, the following occurs during idle periods:
- SSIClk is forced high
- SSIn_FSS is forced high
- The transmit data line SSIn_TX is arbitrarily forced low
- When the SSI is configured as a master, the SSI enables the SSIn_CLK DIO
- When the SSI is configured as a slave, the SSI disables the SSIn_CLK DIO
If the SSI is enabled and valid data is in the TX FIFO, the start of transmission is signified by the SSIn_FSS master signal going low. The master SSIn_TX output DIO is enabled. After an additional one-half SSIn_CLK period, both master and slave data are enabled onto their respective transmission lines. At the same time, SSIn_CLK is enabled with a falling-edge transition. Data is then captured on the rising edges and propagated on the falling edges of the SSIn_CLK signal.
For a single word transmission, after all bits are transferred, the SSIn_FSS line returns to its IDLE high state one SSIn_CLK period after the last bit is captured.
For continuous back-to-back transmissions, the SSIn_FSS pin remains in its active low state until the final bit of the last word is captured and then returns to its IDLE state.
For continuous back-to-back transfers, the SSIn_FSS pin is held low between successive data words and terminates like a single-word transfer.