SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
#AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_TABLE_1 lists the memory-mapped registers for the AUX_ANAIF registers. All register offset addresses not listed in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
Complex bit access types are encoded to fit into small table cells. #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_LEGEND shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
ADCCTL is shown in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_ADCCTL_FIGURE and described in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_ADCCTL_TABLE.
Return to the Summary Table.
ADC Control
Configuration of ADI_4_AUX:ADC0.SMPL_MODE decides if the ADC trigger starts sampling or conversion.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | START_POL | START_SRC | |||||
| R-0h | R/W-0h | R/W-3Fh | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CMD | ||||||
| R-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-15 | RESERVED | R | 0h | Reserved |
| 14 | START_POL | R/W | 0h | Select active polarity for START_SRC event.
0h = Set ADC trigger on rising edge of event source. 1h = Set ADC trigger on falling edge of event source. |
| 13-8 | START_SRC | R/W | 3Fh | Select ADC trigger event source from the asynchronous AUX event bus. Set START_SRC to NO_EVENT if you want to trigger the ADC manually through ADCTRIG.START. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. 0h = AUX_EVCTL:EVSTAT0.AUXIO0 1h = AUX_EVCTL:EVSTAT0.AUXIO1 2h = AUX_EVCTL:EVSTAT0.AUXIO2 3h = AUX_EVCTL:EVSTAT0.AUXIO3 4h = AUX_EVCTL:EVSTAT0.AUXIO4 5h = AUX_EVCTL:EVSTAT0.AUXIO5 6h = AUX_EVCTL:EVSTAT0.AUXIO6 7h = AUX_EVCTL:EVSTAT0.AUXIO7 8h = AUX_EVCTL:EVSTAT0.AUXIO8 9h = AUX_EVCTL:EVSTAT0.AUXIO9 Ah = AUX_EVCTL:EVSTAT0.AUXIO10 Bh = AUX_EVCTL:EVSTAT0.AUXIO11 Ch = AUX_EVCTL:EVSTAT0.AUXIO12 Dh = AUX_EVCTL:EVSTAT0.AUXIO13 Eh = AUX_EVCTL:EVSTAT0.AUXIO14 Fh = AUX_EVCTL:EVSTAT0.AUXIO15 10h = AUX_EVCTL:EVSTAT1.AUXIO16 11h = AUX_EVCTL:EVSTAT1.AUXIO17 12h = AUX_EVCTL:EVSTAT1.AUXIO18 13h = AUX_EVCTL:EVSTAT1.AUXIO19 14h = AUX_EVCTL:EVSTAT1.AUXIO20 15h = AUX_EVCTL:EVSTAT1.AUXIO21 16h = AUX_EVCTL:EVSTAT1.AUXIO22 17h = AUX_EVCTL:EVSTAT1.AUXIO23 18h = AUX_EVCTL:EVSTAT1.AUXIO24 19h = AUX_EVCTL:EVSTAT1.AUXIO25 1Ah = AUX_EVCTL:EVSTAT1.AUXIO26 1Bh = AUX_EVCTL:EVSTAT1.AUXIO27 1Ch = AUX_EVCTL:EVSTAT1.AUXIO28 1Dh = AUX_EVCTL:EVSTAT1.AUXIO29 1Eh = AUX_EVCTL:EVSTAT1.AUXIO30 1Fh = AUX_EVCTL:EVSTAT1.AUXIO31 20h = AUX_EVCTL:EVSTAT2.MANUAL_EV 21h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2 22h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY 23h = AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ 24h = AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD 25h = AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD 26h = AUX_EVCTL:EVSTAT2.SCLK_LF 27h = AUX_EVCTL:EVSTAT2.PWR_DWN 28h = AUX_EVCTL:EVSTAT2.MCU_ACTIVE 29h = AUX_EVCTL:EVSTAT2.VDDR_RECHARGE 2Ah = AUX_EVCTL:EVSTAT2.ACLK_REF 2Bh = AUX_EVCTL:EVSTAT2.MCU_EV 2Eh = AUX_EVCTL:EVSTAT2.AUX_COMPA 2Fh = AUX_EVCTL:EVSTAT2.AUX_COMPB 30h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 31h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 32h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 33h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 34h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE 35h = AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV 36h = AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV 37h = AUX_EVCTL:EVSTAT3.AUX_TDC_DONE 38h = AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N 3Dh = AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE 3Fh = No event. |
| 7-2 | RESERVED | R | 0h | Reserved |
| 1-0 | CMD | R/W | 0h | ADC interface command. Non-enumerated values are not supported. The written value is returned when read. 0h = Disable ADC interface. 1h = Enable ADC interface. 3h = Flush ADC FIFO. |
ADCFIFOSTAT is shown in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_ADCFIFOSTAT_FIGURE and described in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_ADCFIFOSTAT_TABLE.
Return to the Summary Table.
ADC FIFO Status
FIFO can hold up to four ADC samples.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | OVERFLOW | UNDERFLOW | FULL | ALMOST_FULL | EMPTY | ||
| R-0h | R-0h | R-0h | R-0h | R-0h | R-1h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-5 | RESERVED | R | 0h | Reserved |
| 4 | OVERFLOW | R | 0h | FIFO overflow flag. 0: FIFO has not overflowed. 1: FIFO has overflowed, this flag is sticky until you flush the FIFO. When the flag is set, the ADC FIFO write pointer is static. It is not possible to add more samples to the ADC FIFO. Flush FIFO to clear the flag. |
| 3 | UNDERFLOW | R | 0h | FIFO underflow flag. 0: FIFO has not underflowed. 1: FIFO has underflowed, this flag is sticky until you flush the FIFO. When the flag is set, the ADC FIFO read pointer is static. Read returns the previous sample that was read. Flush FIFO to clear the flag. |
| 2 | FULL | R | 0h | FIFO full flag. 0: FIFO is not full, there is less than 4 samples in the FIFO. 1: FIFO is full, there are 4 samples in the FIFO. When the flag is set, it is not possible to add more samples to the ADC FIFO. An attempt to add samples sets the OVERFLOW flag. |
| 1 | ALMOST_FULL | R | 0h | FIFO almost full flag. 0: There are less than 3 samples in the FIFO, or the FIFO is full. The FULL flag is also asserted in the latter case. 1: There are 3 samples in the FIFO, there is room for one more sample. |
| 0 | EMPTY | R | 1h | FIFO empty flag. 0: FIFO contains one or more samples. 1: FIFO is empty. When the flag is set, read returns the previous sample that was read and sets the UNDERFLOW flag. |
ADCFIFO is shown in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_ADCFIFO_FIGURE and described in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_ADCFIFO_TABLE.
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ADC FIFO
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DATA | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-12 | RESERVED | R | 0h | Reserved |
| 11-0 | DATA | R/W | 0h | FIFO data. Read: Get oldest ADC sample from FIFO. Write: Write dummy sample to FIFO. This is useful for code development when you do not have real ADC samples. |
ADCTRIG is shown in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_ADCTRIG_FIGURE and described in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_ADCTRIG_TABLE.
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ADC Trigger
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | START | ||||||
| R-0h | W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-1 | RESERVED | R | 0h | Reserved |
| 0 | START | W | 0h | Manual ADC trigger. Write any value to START to trigger ADC. To manually trigger the ADC, you must set ADCCTL.START_SRC to NO_EVENT to avoid conflict with event-driven ADC trigger. |
ISRCCTL is shown in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_ISRCCTL_FIGURE and described in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_ISRCCTL_TABLE.
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Current Source Control
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESET_N | ||||||
| R-0h | R/W-1h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-1 | RESERVED | R | 0h | Reserved |
| 0 | RESET_N | R/W | 1h | ISRC reset control. 0: ISRC drives 0 uA. 1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN. |
DACCTL is shown in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_DACCTL_FIGURE and described in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_DACCTL_TABLE.
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DAC Control
This register controls the analog part of the DAC.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DAC_EN | DAC_BUFFER_EN | DAC_PRECHARGE_EN | DAC_VOUT_SEL | |||
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-6 | RESERVED | R | 0h | Reserved |
| 5 | DAC_EN | R/W | 0h | DAC module enable. 0: Disable DAC. 1: Enable DAC. The Sensor Controller must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ equals PDA. The System CPU must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ equals PDA in Standby TI-RTOS power mode. The System CPU must set AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to BUS_RATE to use the DAC in Active and Idle TI-RTOS power modes. |
| 4 | DAC_BUFFER_EN | R/W | 0h | DAC buffer enable. DAC buffer reduces the time required to produce the programmed voltage at the expense of increased current consumption. 0: Disable DAC buffer. 1: Enable DAC buffer. Enable buffer when DAC_VOUT_SEL equals COMPA_IN. Do not enable the buffer when AUX_SYSIF:OPMODEREQ.REQ equals PDA or PDLP. |
| 3 | DAC_PRECHARGE_EN | R/W | 0h | DAC precharge enable. Only enable precharge when ADI_4_AUX:MUX2.DAC_VREF_SEL equals DCOUPL and VDDS is higher than 2.65 V. DAC output voltage range: 0: 0 V to 1.28 V. 1: 1.28 V to 2.56 V. Otherwise, see ADI_4_AUX:MUX2.DAC_VREF_SEL for DAC output voltage range. Enable precharge 1 us before you enable the DAC and the buffer. |
| 2-0 | DAC_VOUT_SEL | R/W | 0h | DAC output connection. An analog node must only have one driver. Other drivers for the following analog nodes are configured in [ANATOP_MMAP::ADI_4_AUX:*]. 0h = Connect to nothing 1h = Connect to COMPB_REF analog node. 2h = Connect to COMPA_REF analog node. 4h = Connect to COMPA_IN analog node. |
LPMBIASCTL is shown in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_LPMBIASCTL_FIGURE and described in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_LPMBIASCTL_TABLE.
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Low Power Mode Bias Control
The low power mode bias module provides bias current to DAC and Comparator A when AUX_SYSIF:OPMODEREQ.REQ differers from A.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-0h | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | EN | ||||||||||||||
| R-0h | R/W-0h | ||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-1 | RESERVED | R | 0h | Reserved |
| 0 | EN | R/W | 0h | Module enable. 0: Disable low power mode bias module. 1: Enable low power mode bias module. Set EN to 1 15 us before you enable the DAC or Comparator A. |
DACSMPLCTL is shown in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_DACSMPLCTL_FIGURE and described in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_DACSMPLCTL_TABLE.
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DAC Sample Control
The DAC sample clock maintains the DAC voltage stored in the sample-and-hold capacitor. The DAC sample clock waveform consists of a setup phase followed by a hold phase. In the setup phase the sample-and-hold capacitor charges to the programmed voltage. The hold phase maintains the voltage with minimal power.
DACSMPLCFG0 and DACSMPLCFG1 configure the DAC sample clock waveform.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-0h | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | EN | ||||||||||||||
| R-0h | R/W-0h | ||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-1 | RESERVED | R | 0h | Reserved |
| 0 | EN | R/W | 0h | DAC sample clock enable. 0: Disable sample clock. The sample clock stops low and DACSTAT becomes 0 when the current sample clock period completes. 1: Enable DAC sample clock. DACSTAT must be 0 before you enable sample clock. |
DACSMPLCFG0 is shown in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_DACSMPLCFG0_FIGURE and described in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_DACSMPLCFG0_TABLE.
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DAC Sample Configuration 0
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CLKDIV | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-6 | RESERVED | R | 0h | Reserved |
| 5-0 | CLKDIV | R/W | 0h | Clock division. AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE divided by (CLKDIV + 1) determines the sample clock base frequency. 0: Divide by 1. 1: Divide by 2. ... 63: Divide by 64. |
DACSMPLCFG1 is shown in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_DACSMPLCFG1_FIGURE and described in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_DACSMPLCFG1_TABLE.
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DAC Sample Configuration 1
The sample clock period equals (high time + low time) * base period. DACSMPLCFG0.CLKDIV determines the base period.
Timing requirements (DAC Buffer On / DAC Buffer Off):
- (high time + low time) * base period > (4 us / 1 us)
- (high time * base period) > (2 us / 0.5 us)
- (low time * base period) > (2 us / 0.5 us)
- (low time * base period + HOLD_INTERVAL * sample clock period) < 32 us
If AUX_SYSIF:OPMODEREQ.REQ equals PDLP, you must set:
- H_PER = L_PER = HOLD_INTERVAL = 0.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | H_PER | L_PER | SETUP_CNT | ||||
| R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HOLD_INTERVAL | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-15 | RESERVED | R | 0h | Reserved |
| 14 | H_PER | R/W | 0h | High time. The sample clock period is high for this many base periods. 0: 2 periods 1: 4 periods |
| 13-12 | L_PER | R/W | 0h | Low time. The sample clock period is low for this many base periods. 0: 1 period 1: 2 periods 2: 3 periods 3: 4 periods |
| 11-8 | SETUP_CNT | R/W | 0h | Setup count. Number of active sample clock periods during the setup phase. 0: 1 sample clock period 1: 2 sample clock periods ... 15 : 16 sample clock periods |
| 7-0 | HOLD_INTERVAL | R/W | 0h | Hold interval. Number of inactive sample clock periods between each active sample clock period during hold phase. The sample clock is low when inactive. The range is 0 to 255. |
DACVALUE is shown in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_DACVALUE_FIGURE and described in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_DACVALUE_TABLE.
Return to the Summary Table.
DAC Value
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VALUE | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R | 0h | Reserved |
| 7-0 | VALUE | R/W | 0h | DAC value. Digital data word for the DAC. Only change VALUE when DACCTL.DAC_EN is 0. Then wait 1 us before you enable the DAC. |
DACSTAT is shown in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_DACSTAT_FIGURE and described in #AUX_ANAIF_AUX_ANAIF_MMAP_AUX_ANAIF_AUX_ANAIF_ALL_DACSTAT_TABLE.
Return to the Summary Table.
DAC Status
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SETUP_ACTIVE | HOLD_ACTIVE | |||||
| R-0h | R-0h | R-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-2 | RESERVED | R | 0h | Reserved |
| 1 | SETUP_ACTIVE | R | 0h | DAC setup phase status. 0: Sample clock is disabled or setup phase is complete. 1: Setup phase in progress. |
| 0 | HOLD_ACTIVE | R | 0h | DAC hold phase status. 0: Sample clock is disabled or DAC is not in hold phase. 1: Hold phase in progress. |