SWCU192 User guide | 德州仪器 TI.com.cn

SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

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    2. 849
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      20. 869
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                899
        
                900
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    1. 911
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6. 917
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    3. 922
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7. 925
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    1. 937
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    1. 942
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  11. 951
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  12. 957
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  14. 959
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9. 963
  1. 964
10. 965
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    1. 968
      1. 969
    2. 970
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  5. 976
    1. 977
    2. 978
      1. 979
    3. 980
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    4. 983
      1. 984
      2. 985
    5. 986
      1. 987
      2. 988
      3. 989
  6. 990
    1. 991
    2. 992
11. 993
  1. 994
  2. 995
  3. 996
997

20.8.3 AUX_EVCTL Registers

#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_TABLE_1 lists the memory-mapped registers for the AUX_EVCTL registers. All register offset addresses not listed in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 20-74 AUX_EVCTL Registers

Offset	Acronym	Register Name	Section
0h	EVSTAT0	Event Status 0	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT0
4h	EVSTAT1	Event Status 1	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT1
8h	EVSTAT2	Event Status 2	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT2
Ch	EVSTAT3	Event Status 3	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT3
10h	SCEWEVCFG0	Sensor Controller Engine Wait Event Configuration 0	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_SCEWEVCFG0
14h	SCEWEVCFG1	Sensor Controller Engine Wait Event Configuration 1	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_SCEWEVCFG1
18h	DMACTL	Direct Memory Access Control	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_DMACTL
20h	SWEVSET	Software Event Set	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_SWEVSET
24h	EVTOAONFLAGS	Events To AON Flags	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVTOAONFLAGS
28h	EVTOAONPOL	Events To AON Polarity	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVTOAONPOL
2Ch	EVTOAONFLAGSCLR	Events To AON Clear	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVTOAONFLAGSCLR
30h	EVTOMCUFLAGS	Events to MCU Flags	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVTOMCUFLAGS
34h	EVTOMCUPOL	Event To MCU Polarity	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVTOMCUPOL
38h	EVTOMCUFLAGSCLR	Events To MCU Flags Clear	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVTOMCUFLAGSCLR
3Ch	COMBEVTOMCUMASK	Combined Event To MCU Mask	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_COMBEVTOMCUMASK
40h	EVOBSCFG	Event Observation Configuration	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVOBSCFG
44h	PROGDLY	Programmable Delay	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_PROGDLY
48h	MANUAL	Manual	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_MANUAL
4Ch	EVSTAT0L	Event Status 0 Low	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT0L
50h	EVSTAT0H	Event Status 0 High	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT0H
54h	EVSTAT1L	Event Status 1 Low	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT1L
58h	EVSTAT1H	Event Status 1 High	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT1H
5Ch	EVSTAT2L	Event Status 2 Low	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT2L
60h	EVSTAT2H	Event Status 2 High	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT2H
64h	EVSTAT3L	Event Status 3 Low	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT3L
68h	EVSTAT3H	Event Status 3 High	#AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT3H

Complex bit access types are encoded to fit into small table cells. #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_LEGEND shows the codes that are used for access types in this section.

Table 20-75 AUX_EVCTL Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
W0C	W 0C	Write 0 to clear
Reset or Default Value
-n		Value after reset or the default value

20.8.3.1 EVSTAT0 Register (Offset = 0h) [Reset = 00000000h]

EVSTAT0 is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT0_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT0_TABLE.

Return to the Summary Table.

Event Status 0
Register holds events 0 thru 15 of the 64-bit event bus that is synchronous to AUX clock. All events read through this register are synchronized at SCE clock rate, unless otherwise noted. The following subscribers use the asynchronous version of events in this register.
- AUX_TIMER2.
- AUX_ANAIF.
- AUX_TDC.
- AUX_SYSIF.
- AUX_AIODIOn.
- EVOBSCFG.

Figure 20-66 EVSTAT0 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
AUXIO15	AUXIO14	AUXIO13	AUXIO12	AUXIO11	AUXIO10	AUXIO9	AUXIO8
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
AUXIO7	AUXIO6	AUXIO5	AUXIO4	AUXIO3	AUXIO2	AUXIO1	AUXIO0
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 20-76 EVSTAT0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	AUXIO15	R	0h	AUXIO15 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 7.
14	AUXIO14	R	0h	AUXIO14 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 6.
13	AUXIO13	R	0h	AUXIO13 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 5.
12	AUXIO12	R	0h	AUXIO12 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 4.
11	AUXIO11	R	0h	AUXIO11 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 3.
10	AUXIO10	R	0h	AUXIO10 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 2.
9	AUXIO9	R	0h	AUXIO9 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 1.
8	AUXIO8	R	0h	AUXIO8 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 0.
7	AUXIO7	R	0h	AUXIO7 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 7.
6	AUXIO6	R	0h	AUXIO6 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 6.
5	AUXIO5	R	0h	AUXIO5 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 5.
4	AUXIO4	R	0h	AUXIO4 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 4.
3	AUXIO3	R	0h	AUXIO3 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 3.
2	AUXIO2	R	0h	AUXIO2 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 2.
1	AUXIO1	R	0h	AUXIO1 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 1.
0	AUXIO0	R	0h	AUXIO0 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 0.

20.8.3.2 EVSTAT1 Register (Offset = 4h) [Reset = 00000000h]

EVSTAT1 is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT1_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT1_TABLE.

Return to the Summary Table.

Event Status 1
Register holds events 16 thru 31 of the 64-bit event bus that is synchronous to AUX clock. All events read through this register are synchronized at SCE clock rate, unless otherwise noted. The following subscribers use the asynchronous version of events in this register.
- AUX_TIMER2.
- AUX_ANAIF.
- AUX_TDC.
- AUX_SYSIF.
- AUX_AIODIOn.
- EVOBSCFG.

Figure 20-67 EVSTAT1 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
AUXIO31	AUXIO30	AUXIO29	AUXIO28	AUXIO27	AUXIO26	AUXIO25	AUXIO24
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
AUXIO23	AUXIO22	AUXIO21	AUXIO20	AUXIO19	AUXIO18	AUXIO17	AUXIO16
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 20-77 EVSTAT1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	AUXIO31	R	0h	AUXIO31 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 7.
14	AUXIO30	R	0h	AUXIO30 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 6.
13	AUXIO29	R	0h	AUXIO29 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 5.
12	AUXIO28	R	0h	AUXIO28 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 4.
11	AUXIO27	R	0h	AUXIO27 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 3.
10	AUXIO26	R	0h	AUXIO26 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 2.
9	AUXIO25	R	0h	AUXIO25 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 1.
8	AUXIO24	R	0h	AUXIO24 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 0.
7	AUXIO23	R	0h	AUXIO23 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 7.
6	AUXIO22	R	0h	AUXIO22 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 6.
5	AUXIO21	R	0h	AUXIO21 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 5.
4	AUXIO20	R	0h	AUXIO20 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 4.
3	AUXIO19	R	0h	AUXIO19 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 3.
2	AUXIO18	R	0h	AUXIO18 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 2.
1	AUXIO17	R	0h	AUXIO17 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 1.
0	AUXIO16	R	0h	AUXIO16 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 0.

20.8.3.3 EVSTAT2 Register (Offset = 8h) [Reset = 00000000h]

EVSTAT2 is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT2_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT2_TABLE.

Return to the Summary Table.

Event Status 2
Register holds events 32 thru 47 of the 64-bit event bus that is synchronous to AUX clock. All events read through this register are synchronized at SCE clock rate, unless otherwise noted. The following subscribers use the asynchronous version of events in this register.
- AUX_TIMER2.
- AUX_ANAIF.
- AUX_TDC.
- AUX_SYSIF.
- AUX_AIODIOn.
- EVOBSCFG.

Figure 20-68 EVSTAT2 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
AUX_COMPB	AUX_COMPA	MCU_OBSMUX1	MCU_OBSMUX0	MCU_EV	ACLK_REF	VDDR_RECHARGE	MCU_ACTIVE
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
PWR_DWN	SCLK_LF	AON_BATMON_TEMP_UPD	AON_BATMON_BAT_UPD	AON_RTC_4KHZ	AON_RTC_CH2_DLY	AON_RTC_CH2	MANUAL_EV
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 20-78 EVSTAT2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	AUX_COMPB	R	0h	Comparator B output. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPB_SYNC_RATE sets the synchronization rate for this event.
14	AUX_COMPA	R	0h	Comparator A output. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPA_SYNC_RATE sets the synchronization rate for this event.
13	MCU_OBSMUX1	R	0h	Observation input 1 from IOC. This event is configured by IOC:OBSAUXOUTPUT.SEL1.
12	MCU_OBSMUX0	R	0h	Observation input 0 from IOC. This event is configured by IOC:OBSAUXOUTPUT.SEL0 and can be overridden by IOC:OBSAUXOUTPUT.SEL_MISC.
11	MCU_EV	R	0h	Event from EVENT configured by EVENT:AUXSEL0.
10	ACLK_REF	R	0h	TDC reference clock. It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by AUX_SYSIF:TDCREFCLKCTL.REQ.
9	VDDR_RECHARGE	R	0h	Event is high during VDDR recharge.
8	MCU_ACTIVE	R	0h	Event is high while system(MCU, AUX, or JTAG domains) is active or transitions to active (GLDO or DCDC power supply state). Event is not high during VDDR recharge.
7	PWR_DWN	R	0h	Event is high while system(MCU, AUX, or JTAG domains) is in powerdown (uLDO power supply).
6	SCLK_LF	R	0h	SCLK_LF clock
5	AON_BATMON_TEMP_UPD	R	0h	Event is high for two SCLK_MF clock periods when there is an update of AON_BATMON:TEMP.
4	AON_BATMON_BAT_UPD	R	0h	Event is high for two SCLK_MF clock periods when there is an update of AON_BATMON:BAT.
3	AON_RTC_4KHZ	R	0h	AON_RTC:SUBSEC.VALUE bit 19. AON_RTC:CTL.RTC_4KHZ_EN enables this event.
2	AON_RTC_CH2_DLY	R	0h	AON_RTC:EVFLAGS.CH2 delayed by AON_RTC:CTL.EV_DELAY configuration.
1	AON_RTC_CH2	R	0h	AON_RTC:EVFLAGS.CH2.
0	MANUAL_EV	R	0h	Programmable event. See MANUAL for description.

20.8.3.4 EVSTAT3 Register (Offset = Ch) [Reset = 00000000h]

EVSTAT3 is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT3_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT3_TABLE.

Return to the Summary Table.

Event Status 3
Register holds events 48 thru 63 of the 64-bit event bus that is synchronous to AUX clock. All events read through this register are synchronized at SCE clock rate, unless otherwise noted. The following subscribers use the asynchronous version of events in this register.
- AUX_TIMER2.
- AUX_ANAIF.
- AUX_TDC .
- AUX_SYSIF.
- AUX_AIODIOn.
- EVOBSCFG.

Figure 20-69 EVSTAT3 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
AUX_TIMER2_CLKSWITCH_RDY	AUX_DAC_HOLD_ACTIVE	AUX_SMPH_AUTOTAKE_DONE	AUX_ADC_FIFO_NOT_EMPTY	AUX_ADC_FIFO_ALMOST_FULL	AUX_ADC_IRQ	AUX_ADC_DONE	AUX_ISRC_RESET_N
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
AUX_TDC_DONE	AUX_TIMER0_EV	AUX_TIMER1_EV	AUX_TIMER2_PULSE	AUX_TIMER2_EV3	AUX_TIMER2_EV2	AUX_TIMER2_EV1	AUX_TIMER2_EV0
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 20-79 EVSTAT3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	AUX_TIMER2_CLKSWITCH_RDY	R	0h	AUX_SYSIF:TIMER2CLKSWITCH.RDY
14	AUX_DAC_HOLD_ACTIVE	R	0h	AUX_ANAIF:DACSTAT.HOLD_ACTIVE
13	AUX_SMPH_AUTOTAKE_DONE	R	0h	See AUX_SMPH:AUTOTAKE.SMPH_ID for description.
12	AUX_ADC_FIFO_NOT_EMPTY	R	0h	AUX_ANAIF:ADCFIFOSTAT.EMPTY negated
11	AUX_ADC_FIFO_ALMOST_FULL	R	0h	AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL
10	AUX_ADC_IRQ	R	0h	The logical function for this event is configurable. When DMACTL.EN = 1 : Event = UDMA0 Channel 7 done event OR AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW When DMACTL.EN = 0 : Event = (NOT AUX_ANAIF:ADCFIFOSTAT.EMPTY) OR AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW Bit 7 in UDMA0:DONEMASK must be 0.
9	AUX_ADC_DONE	R	0h	AUX_ANAIF ADC conversion done event. Event is synchronized at AUX bus rate.
8	AUX_ISRC_RESET_N	R	0h	AUX_ANAIF:ISRCCTL.RESET_N
7	AUX_TDC_DONE	R	0h	AUX_TDC:STAT.DONE
6	AUX_TIMER0_EV	R	0h	AUX_TIMER0_EV event, see AUX_TIMER01:T0TARGET for description.
5	AUX_TIMER1_EV	R	0h	AUX_TIMER1_EV event, see AUX_TIMER01:T1TARGET for description.
4	AUX_TIMER2_PULSE	R	0h	AUX_TIMER2 pulse event. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event.
3	AUX_TIMER2_EV3	R	0h	AUX_TIMER2 event output 3. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event.
2	AUX_TIMER2_EV2	R	0h	AUX_TIMER2 event output 2. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event.
1	AUX_TIMER2_EV1	R	0h	AUX_TIMER2 event output 1. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event.
0	AUX_TIMER2_EV0	R	0h	AUX_TIMER2 event output 0. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event.

20.8.3.5 SCEWEVCFG0 Register (Offset = 10h) [Reset = 00000000h]

SCEWEVCFG0 is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_SCEWEVCFG0_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_SCEWEVCFG0_TABLE.

Return to the Summary Table.

Sensor Controller Engine Wait Event Configuration 0
Configuration of this register and SCEWEVCFG1 controls bit index 7 in AUX_SCE:WUSTAT.EV_SIGNALS. This bit can be used by AUX_SCE WEV0, WEV1, BEV0 and BEV1 instructions.
When COMB_EV_EN = 0:
AUX_SCE:WUSTAT.EV_SIGNALS (7) = EV0_SEL event
When COMB_EV_EN = 1:
AUX_SCE:WUSTAT.EV_SIGNALS (7) = ( EV0_SEL event ) OR ( SCEWEVCFG1.EV1_SEL event )
Bit fields SCEWEVCFG1.EV0_POL and SCEWEVCFG1.EV1_POL control the polarity of selected events.
Event combination is useful when there is a need to wait for a certain condition with timeout.

Figure 20-70 SCEWEVCFG0 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED	COMB_EV_EN	EV0_SEL
R-0h	R/W-0h	R/W-0h

Table 20-80 SCEWEVCFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6	COMB_EV_EN	R/W	0h	Event combination control: 0: Disable event combination. 1: Enable event combination.
5-0	EV0_SEL	R/W	0h	Select the event source from the synchronous event bus to be used in event equation. 0h = EVSTAT0.AUXIO0 1h = EVSTAT0.AUXIO1 2h = EVSTAT0.AUXIO2 3h = EVSTAT0.AUXIO3 4h = EVSTAT0.AUXIO4 5h = EVSTAT0.AUXIO5 6h = EVSTAT0.AUXIO6 7h = EVSTAT0.AUXIO7 8h = EVSTAT0.AUXIO8 9h = EVSTAT0.AUXIO9 Ah = EVSTAT0.AUXIO10 Bh = EVSTAT0.AUXIO11 Ch = EVSTAT0.AUXIO12 Dh = EVSTAT0.AUXIO13 Eh = EVSTAT0.AUXIO14 Fh = EVSTAT0.AUXIO15 10h = EVSTAT1.AUXIO16 11h = EVSTAT1.AUXIO17 12h = EVSTAT1.AUXIO18 13h = EVSTAT1.AUXIO19 14h = EVSTAT1.AUXIO20 15h = EVSTAT1.AUXIO21 16h = EVSTAT1.AUXIO22 17h = EVSTAT1.AUXIO23 18h = EVSTAT1.AUXIO24 19h = EVSTAT1.AUXIO25 1Ah = EVSTAT1.AUXIO26 1Bh = EVSTAT1.AUXIO27 1Ch = EVSTAT1.AUXIO28 1Dh = EVSTAT1.AUXIO29 1Eh = EVSTAT1.AUXIO30 1Fh = EVSTAT1.AUXIO31 20h = Programmable delay event as described in PROGDLY 21h = EVSTAT2.AON_RTC_CH2 22h = EVSTAT2.AON_RTC_CH2_DLY 23h = EVSTAT2.AON_RTC_4KHZ 24h = EVSTAT2.AON_BATMON_BAT_UPD 25h = EVSTAT2.AON_BATMON_TEMP_UPD 26h = EVSTAT2.SCLK_LF 27h = EVSTAT2.PWR_DWN 28h = EVSTAT2.MCU_ACTIVE 29h = EVSTAT2.VDDR_RECHARGE 2Ah = EVSTAT2.ACLK_REF 2Bh = EVSTAT2.MCU_EV 2Ch = EVSTAT2.MCU_OBSMUX0 2Dh = EVSTAT2.MCU_OBSMUX1 2Eh = EVSTAT2.AUX_COMPA 2Fh = EVSTAT2.AUX_COMPB 30h = EVSTAT3.AUX_TIMER2_EV0 31h = EVSTAT3.AUX_TIMER2_EV1 32h = EVSTAT3.AUX_TIMER2_EV2 33h = EVSTAT3.AUX_TIMER2_EV3 34h = EVSTAT3.AUX_TIMER2_PULSE 35h = EVSTAT3.AUX_TIMER1_EV 36h = EVSTAT3.AUX_TIMER0_EV 37h = EVSTAT3.AUX_TDC_DONE 38h = EVSTAT3.AUX_ISRC_RESET_N 39h = EVSTAT3.AUX_ADC_DONE 3Ah = EVSTAT3.AUX_ADC_IRQ 3Bh = EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL 3Ch = EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY 3Dh = EVSTAT3.AUX_SMPH_AUTOTAKE_DONE 3Eh = EVSTAT3.AUX_DAC_HOLD_ACTIVE 3Fh = EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY

Bit

Field

Type

Reset

Description

31-7

RESERVED

Reserved

COMB_EV_EN

R/W

Event combination control:
0: Disable event combination.
1: Enable event combination.

5-0

EV0_SEL

R/W

Select the event source from the synchronous event bus to be used in event equation.

0h = EVSTAT0.AUXIO0

1h = EVSTAT0.AUXIO1

2h = EVSTAT0.AUXIO2

3h = EVSTAT0.AUXIO3

4h = EVSTAT0.AUXIO4

5h = EVSTAT0.AUXIO5

6h = EVSTAT0.AUXIO6

7h = EVSTAT0.AUXIO7

8h = EVSTAT0.AUXIO8

9h = EVSTAT0.AUXIO9

Ah = EVSTAT0.AUXIO10

Bh = EVSTAT0.AUXIO11

Ch = EVSTAT0.AUXIO12

Dh = EVSTAT0.AUXIO13

Eh = EVSTAT0.AUXIO14

Fh = EVSTAT0.AUXIO15

10h = EVSTAT1.AUXIO16

11h = EVSTAT1.AUXIO17

12h = EVSTAT1.AUXIO18

13h = EVSTAT1.AUXIO19

14h = EVSTAT1.AUXIO20

15h = EVSTAT1.AUXIO21

16h = EVSTAT1.AUXIO22

17h = EVSTAT1.AUXIO23

18h = EVSTAT1.AUXIO24

19h = EVSTAT1.AUXIO25

1Ah = EVSTAT1.AUXIO26

1Bh = EVSTAT1.AUXIO27

1Ch = EVSTAT1.AUXIO28

1Dh = EVSTAT1.AUXIO29

1Eh = EVSTAT1.AUXIO30

1Fh = EVSTAT1.AUXIO31

20h = Programmable delay event as described in PROGDLY

21h = EVSTAT2.AON_RTC_CH2

22h = EVSTAT2.AON_RTC_CH2_DLY

23h = EVSTAT2.AON_RTC_4KHZ

24h = EVSTAT2.AON_BATMON_BAT_UPD

25h = EVSTAT2.AON_BATMON_TEMP_UPD

26h = EVSTAT2.SCLK_LF

27h = EVSTAT2.PWR_DWN

28h = EVSTAT2.MCU_ACTIVE

29h = EVSTAT2.VDDR_RECHARGE

2Ah = EVSTAT2.ACLK_REF

2Bh = EVSTAT2.MCU_EV

2Ch = EVSTAT2.MCU_OBSMUX0

2Dh = EVSTAT2.MCU_OBSMUX1

2Eh = EVSTAT2.AUX_COMPA

2Fh = EVSTAT2.AUX_COMPB

30h = EVSTAT3.AUX_TIMER2_EV0

31h = EVSTAT3.AUX_TIMER2_EV1

32h = EVSTAT3.AUX_TIMER2_EV2

33h = EVSTAT3.AUX_TIMER2_EV3

34h = EVSTAT3.AUX_TIMER2_PULSE

35h = EVSTAT3.AUX_TIMER1_EV

36h = EVSTAT3.AUX_TIMER0_EV

37h = EVSTAT3.AUX_TDC_DONE

38h = EVSTAT3.AUX_ISRC_RESET_N

39h = EVSTAT3.AUX_ADC_DONE

3Ah = EVSTAT3.AUX_ADC_IRQ

3Bh = EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL

3Ch = EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY

3Dh = EVSTAT3.AUX_SMPH_AUTOTAKE_DONE

3Eh = EVSTAT3.AUX_DAC_HOLD_ACTIVE

3Fh = EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY

20.8.3.6 SCEWEVCFG1 Register (Offset = 14h) [Reset = 00000000h]

SCEWEVCFG1 is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_SCEWEVCFG1_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_SCEWEVCFG1_TABLE.

Return to the Summary Table.

Sensor Controller Engine Wait Event Configuration 1
See SCEWEVCFG0 for description.

Figure 20-71 SCEWEVCFG1 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
EV0_POL	EV1_POL	EV1_SEL
R/W-0h	R/W-0h	R/W-0h

Table 20-81 SCEWEVCFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	EV0_POL	R/W	0h	Polarity of SCEWEVCFG0.EV0_SEL event. When SCEWEVCFG0.COMB_EV_EN is 0: 0: Non-inverted. 1: Non-inverted. When SCEWEVCFG0.COMB_EV_EN is 1. 0: Non-inverted. 1: Inverted.
6	EV1_POL	R/W	0h	Polarity of EV1_SEL event. When SCEWEVCFG0.COMB_EV_EN is 0: 0: Non-inverted. 1: Non-inverted. When SCEWEVCFG0.COMB_EV_EN is 1. 0: Non-inverted. 1: Inverted.
5-0	EV1_SEL	R/W	0h	Select the event source from the synchronous event bus to be used in event equation. 0h = EVSTAT0.AUXIO0 1h = EVSTAT0.AUXIO1 2h = EVSTAT0.AUXIO2 3h = EVSTAT0.AUXIO3 4h = EVSTAT0.AUXIO4 5h = EVSTAT0.AUXIO5 6h = EVSTAT0.AUXIO6 7h = EVSTAT0.AUXIO7 8h = EVSTAT0.AUXIO8 9h = EVSTAT0.AUXIO9 Ah = EVSTAT0.AUXIO10 Bh = EVSTAT0.AUXIO11 Ch = EVSTAT0.AUXIO12 Dh = EVSTAT0.AUXIO13 Eh = EVSTAT0.AUXIO14 Fh = EVSTAT0.AUXIO15 10h = EVSTAT1.AUXIO16 11h = EVSTAT1.AUXIO17 12h = EVSTAT1.AUXIO18 13h = EVSTAT1.AUXIO19 14h = EVSTAT1.AUXIO20 15h = EVSTAT1.AUXIO21 16h = EVSTAT1.AUXIO22 17h = EVSTAT1.AUXIO23 18h = EVSTAT1.AUXIO24 19h = EVSTAT1.AUXIO25 1Ah = EVSTAT1.AUXIO26 1Bh = EVSTAT1.AUXIO27 1Ch = EVSTAT1.AUXIO28 1Dh = EVSTAT1.AUXIO29 1Eh = EVSTAT1.AUXIO30 1Fh = EVSTAT1.AUXIO31 20h = Programmable delay event as described in PROGDLY 21h = EVSTAT2.AON_RTC_CH2 22h = EVSTAT2.AON_RTC_CH2_DLY 23h = EVSTAT2.AON_RTC_4KHZ 24h = EVSTAT2.AON_BATMON_BAT_UPD 25h = EVSTAT2.AON_BATMON_TEMP_UPD 26h = EVSTAT2.SCLK_LF 27h = EVSTAT2.PWR_DWN 28h = EVSTAT2.MCU_ACTIVE 29h = EVSTAT2.VDDR_RECHARGE 2Ah = EVSTAT2.ACLK_REF 2Bh = EVSTAT2.MCU_EV 2Ch = EVSTAT2.MCU_OBSMUX0 2Dh = EVSTAT2.MCU_OBSMUX1 2Eh = EVSTAT2.AUX_COMPA 2Fh = EVSTAT2.AUX_COMPB 30h = EVSTAT3.AUX_TIMER2_EV0 31h = EVSTAT3.AUX_TIMER2_EV1 32h = EVSTAT3.AUX_TIMER2_EV2 33h = EVSTAT3.AUX_TIMER2_EV3 34h = EVSTAT3.AUX_TIMER2_PULSE 35h = EVSTAT3.AUX_TIMER1_EV 36h = EVSTAT3.AUX_TIMER0_EV 37h = EVSTAT3.AUX_TDC_DONE 38h = EVSTAT3.AUX_ISRC_RESET_N 39h = EVSTAT3.AUX_ADC_DONE 3Ah = EVSTAT3.AUX_ADC_IRQ 3Bh = EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL 3Ch = EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY 3Dh = EVSTAT3.AUX_SMPH_AUTOTAKE_DONE 3Eh = EVSTAT3.AUX_DAC_HOLD_ACTIVE 3Fh = EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY

20.8.3.7 DMACTL Register (Offset = 18h) [Reset = 00000000h]

DMACTL is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_DMACTL_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_DMACTL_TABLE.

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Direct Memory Access Control

Figure 20-72 DMACTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					REQ_MODE	EN	SEL
R-0h					R/W-0h	R/W-0h	R/W-0h

Table 20-82 DMACTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	REQ_MODE	R/W	0h	UDMA0 Request mode 0h = Burst requests are generated on UDMA0 channel 7 when the condition configured in SEL is met. 1h = Single requests are generated on UDMA0 channel 7 when the condition configured in SEL is met.
1	EN	R/W	0h	uDMA ADC interface enable. 0: Disable UDMA0 interface to ADC. 1: Enable UDMA0 interface to ADC.
0	SEL	R/W	0h	Select FIFO watermark level required to trigger a UDMA0 transfer of ADC FIFO data. 0h = UDMA0 trigger event will be generated when there are samples in the ADC FIFO. 1h = UDMA0 trigger event will be generated when the ADC FIFO is almost full (3/4 full).

20.8.3.8 SWEVSET Register (Offset = 20h) [Reset = 00000000h]

SWEVSET is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_SWEVSET_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_SWEVSET_TABLE.

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Software Event Set
Set software event flags from AUX domain to AON and MCU domains. CPUs in MCU domain can read the event flags from EVTOAONFLAGS and clear them in EVTOAONFLAGSCLR.
Use of these event flags is software-defined.

Figure 20-73 SWEVSET Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					SWEV2	SWEV1	SWEV0
R-0h					W-0h	W-0h	W-0h

Table 20-83 SWEVSET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	SWEV2	W	0h	Software event flag 2. 0: No effect. 1: Set software event flag 2.
1	SWEV1	W	0h	Software event flag 1. 0: No effect. 1: Set software event flag 1.
0	SWEV0	W	0h	Software event flag 0. 0: No effect. 1: Set software event flag 0.

20.8.3.9 EVTOAONFLAGS Register (Offset = 24h) [Reset = 00000000h]

EVTOAONFLAGS is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVTOAONFLAGS_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVTOAONFLAGS_TABLE.

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Events To AON Flags
This register contains a collection of event flags routed to AON_EVENT.
To clear an event flag, write to EVTOAONFLAGSCLR or write 0 to event flag in this register.

Figure 20-74 EVTOAONFLAGS Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							AUX_TIMER1_EV
R-0h							R/W0C-0h

7	6	5	4	3	2	1	0
AUX_TIMER0_EV	AUX_TDC_DONE	AUX_ADC_DONE	AUX_COMPB	AUX_COMPA	SWEV2	SWEV1	SWEV0
R/W0C-0h	R/W0C-0h	R/W0C-0h	R/W0C-0h	R/W0C-0h	R/W0C-0h	R/W0C-0h	R/W0C-0h

Table 20-84 EVTOAONFLAGS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	AUX_TIMER1_EV	R/W0C	0h	This event flag is set when level selected by EVTOAONPOL.AUX_TIMER1_EV occurs on EVSTAT3.AUX_TIMER1_EV.
7	AUX_TIMER0_EV	R/W0C	0h	This event flag is set when level selected by EVTOAONPOL.AUX_TIMER0_EV occurs on EVSTAT3.AUX_TIMER0_EV.
6	AUX_TDC_DONE	R/W0C	0h	This event flag is set when level selected by EVTOAONPOL.AUX_TDC_DONE occurs on EVSTAT3.AUX_TDC_DONE.
5	AUX_ADC_DONE	R/W0C	0h	This event flag is set when level selected by EVTOAONPOL.AUX_ADC_DONE occurs on EVSTAT3.AUX_ADC_DONE.
4	AUX_COMPB	R/W0C	0h	This event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on EVSTAT2.AUX_COMPB.
3	AUX_COMPA	R/W0C	0h	This event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on EVSTAT2.AUX_COMPA.
2	SWEV2	R/W0C	0h	This event flag is set when software writes a 1 to SWEVSET.SWEV2.
1	SWEV1	R/W0C	0h	This event flag is set when software writes a 1 to SWEVSET.SWEV1.
0	SWEV0	R/W0C	0h	This event flag is set when software writes a 1 to SWEVSET.SWEV0.

20.8.3.10 EVTOAONPOL Register (Offset = 28h) [Reset = 00000000h]

EVTOAONPOL is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVTOAONPOL_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVTOAONPOL_TABLE.

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Events To AON Polarity
Event source polarity configuration for EVTOAONFLAGS.

Figure 20-75 EVTOAONPOL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							AUX_TIMER1_EV
R-0h							R/W-0h

7	6	5	4	3	2	1	0
AUX_TIMER0_EV	AUX_TDC_DONE	AUX_ADC_DONE	AUX_COMPB	AUX_COMPA	RESERVED
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R-0h

Table 20-85 EVTOAONPOL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	AUX_TIMER1_EV	R/W	0h	Select the level of EVSTAT3.AUX_TIMER1_EV that sets EVTOAONFLAGS.AUX_TIMER1_EV. 0h = High level 1h = Low level
7	AUX_TIMER0_EV	R/W	0h	Select the level of EVSTAT3.AUX_TIMER0_EV that sets EVTOAONFLAGS.AUX_TIMER0_EV. 0h = High level 1h = Low level
6	AUX_TDC_DONE	R/W	0h	Select level of EVSTAT3.AUX_TDC_DONE that sets EVTOAONFLAGS.AUX_TDC_DONE. 0h = High level 1h = Low level
5	AUX_ADC_DONE	R/W	0h	Select the level of EVSTAT3.AUX_ADC_DONE that sets EVTOAONFLAGS.AUX_ADC_DONE. 0h = High level 1h = Low level
4	AUX_COMPB	R/W	0h	Select the edge of EVSTAT2.AUX_COMPB that sets EVTOAONFLAGS.AUX_COMPB. 0h = Rising edge 1h = Falling edge
3	AUX_COMPA	R/W	0h	Select the edge of EVSTAT2.AUX_COMPA that sets EVTOAONFLAGS.AUX_COMPA. 0h = Rising edge 1h = Falling edge
2-0	RESERVED	R	0h	Reserved

20.8.3.11 EVTOAONFLAGSCLR Register (Offset = 2Ch) [Reset = 00000000h]

EVTOAONFLAGSCLR is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVTOAONFLAGSCLR_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVTOAONFLAGSCLR_TABLE.

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Events To AON Clear
Clear event flags in EVTOAONFLAGS.
In order to clear a level sensitive event flag, the event must be deasserted.

Figure 20-76 EVTOAONFLAGSCLR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							AUX_TIMER1_EV
R-0h							W-0h

7	6	5	4	3	2	1	0
AUX_TIMER0_EV	AUX_TDC_DONE	AUX_ADC_DONE	AUX_COMPB	AUX_COMPA	SWEV2	SWEV1	SWEV0
W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h

Table 20-86 EVTOAONFLAGSCLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	AUX_TIMER1_EV	W	0h	Write 1 to clear EVTOAONFLAGS.AUX_TIMER1_EV. Read value is 0.
7	AUX_TIMER0_EV	W	0h	Write 1 to clear EVTOAONFLAGS.AUX_TIMER0_EV. Read value is 0.
6	AUX_TDC_DONE	W	0h	Write 1 to clear EVTOAONFLAGS.AUX_TDC_DONE. Read value is 0.
5	AUX_ADC_DONE	W	0h	Write 1 to clear EVTOAONFLAGS.AUX_ADC_DONE. Read value is 0.
4	AUX_COMPB	W	0h	Write 1 to clear EVTOAONFLAGS.AUX_COMPB. Read value is 0.
3	AUX_COMPA	W	0h	Write 1 to clear EVTOAONFLAGS.AUX_COMPA. Read value is 0.
2	SWEV2	W	0h	Write 1 to clear EVTOAONFLAGS.SWEV2. Read value is 0.
1	SWEV1	W	0h	Write 1 to clear EVTOAONFLAGS.SWEV1. Read value is 0.
0	SWEV0	W	0h	Write 1 to clear EVTOAONFLAGS.SWEV0. Read value is 0.

20.8.3.12 EVTOMCUFLAGS Register (Offset = 30h) [Reset = 00000000h]

EVTOMCUFLAGS is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVTOMCUFLAGS_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVTOMCUFLAGS_TABLE.

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Events to MCU Flags
This register contains a collection of event flags routed to MCU domain.
To clear an event flag, write to EVTOMCUFLAGSCLR or write 0 to event flag in this register. Follow procedure described in AUX_SYSIF:WUCLR to clear AUX_WU_EV event flag.

Figure 20-77 EVTOMCUFLAGS Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
AUX_TIMER2_PULSE	AUX_TIMER2_EV3	AUX_TIMER2_EV2	AUX_TIMER2_EV1	AUX_TIMER2_EV0	AUX_ADC_IRQ	MCU_OBSMUX0	AUX_ADC_FIFO_ALMOST_FULL
R/W0C-0h	R/W0C-0h	R/W0C-0h	R/W0C-0h	R/W0C-0h	R/W0C-0h	R/W0C-0h	R/W0C-0h

7	6	5	4	3	2	1	0
AUX_ADC_DONE	AUX_SMPH_AUTOTAKE_DONE	AUX_TIMER1_EV	AUX_TIMER0_EV	AUX_TDC_DONE	AUX_COMPB	AUX_COMPA	AUX_WU_EV
R/W0C-0h	R/W0C-0h	R/W0C-0h	R/W0C-0h	R/W0C-0h	R/W0C-0h	R/W0C-0h	R/W0C-0h

Table 20-87 EVTOMCUFLAGS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	AUX_TIMER2_PULSE	R/W0C	0h	This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_PULSE occurs on EVSTAT3.AUX_TIMER2_PULSE.
14	AUX_TIMER2_EV3	R/W0C	0h	This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV3 occurs on EVSTAT3.AUX_TIMER2_EV3.
13	AUX_TIMER2_EV2	R/W0C	0h	This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV2 occurs on EVSTAT3.AUX_TIMER2_EV2.
12	AUX_TIMER2_EV1	R/W0C	0h	This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV1 occurs on EVSTAT3.AUX_TIMER2_EV1.
11	AUX_TIMER2_EV0	R/W0C	0h	This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV0 occurs on EVSTAT3.AUX_TIMER2_EV0.
10	AUX_ADC_IRQ	R/W0C	0h	This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_IRQ occurs on EVSTAT3.AUX_ADC_IRQ.
9	MCU_OBSMUX0	R/W0C	0h	This event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs on EVSTAT2.MCU_OBSMUX0.
8	AUX_ADC_FIFO_ALMOST_FULL	R/W0C	0h	This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_FIFO_ALMOST_FULL occurs on EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL.
7	AUX_ADC_DONE	R/W0C	0h	This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_DONE occurs on EVSTAT3.AUX_ADC_DONE.
6	AUX_SMPH_AUTOTAKE_DONE	R/W0C	0h	This event flag is set when level selected by EVTOMCUPOL.AUX_SMPH_AUTOTAKE_DONE occurs on EVSTAT3.AUX_SMPH_AUTOTAKE_DONE.
5	AUX_TIMER1_EV	R/W0C	0h	This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER1_EV occurs on EVSTAT3.AUX_TIMER1_EV.
4	AUX_TIMER0_EV	R/W0C	0h	This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER0_EV occurs on EVSTAT3.AUX_TIMER0_EV.
3	AUX_TDC_DONE	R/W0C	0h	This event flag is set when level selected by EVTOMCUPOL.AUX_TDC_DONE occurs on EVSTAT3.AUX_TDC_DONE.
2	AUX_COMPB	R/W0C	0h	This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on EVSTAT2.AUX_COMPB.
1	AUX_COMPA	R/W0C	0h	This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on EVSTAT2.AUX_COMPA.
0	AUX_WU_EV	R/W0C	0h	This event flag is set when level selected by EVTOMCUPOL.AUX_WU_EV occurs on reduction-OR of the AUX_SYSIF:WUFLAGS register.

20.8.3.13 EVTOMCUPOL Register (Offset = 34h) [Reset = 00000000h]

EVTOMCUPOL is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVTOMCUPOL_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVTOMCUPOL_TABLE.

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Event To MCU Polarity
Event source polarity configuration for EVTOMCUFLAGS.

Figure 20-78 EVTOMCUPOL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
AUX_TIMER2_PULSE	AUX_TIMER2_EV3	AUX_TIMER2_EV2	AUX_TIMER2_EV1	AUX_TIMER2_EV0	AUX_ADC_IRQ	MCU_OBSMUX0	AUX_ADC_FIFO_ALMOST_FULL
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
AUX_ADC_DONE	AUX_SMPH_AUTOTAKE_DONE	AUX_TIMER1_EV	AUX_TIMER0_EV	AUX_TDC_DONE	AUX_COMPB	AUX_COMPA	AUX_WU_EV
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 20-88 EVTOMCUPOL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	AUX_TIMER2_PULSE	R/W	0h	Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_PULSE. 0h = High level 1h = Low level
14	AUX_TIMER2_EV3	R/W	0h	Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV3. 0h = High level 1h = Low level
13	AUX_TIMER2_EV2	R/W	0h	Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV2. 0h = High level 1h = Low level
12	AUX_TIMER2_EV1	R/W	0h	Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV1. 0h = High level 1h = Low level
11	AUX_TIMER2_EV0	R/W	0h	Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV0. 0h = High level 1h = Low level
10	AUX_ADC_IRQ	R/W	0h	Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_IRQ. 0h = High level 1h = Low level
9	MCU_OBSMUX0	R/W	0h	Select the event source level that sets EVTOMCUFLAGS.MCU_OBSMUX0. 0h = High level 1h = Low level
8	AUX_ADC_FIFO_ALMOST_FULL	R/W	0h	Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL. 0h = High level 1h = Low level
7	AUX_ADC_DONE	R/W	0h	Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_DONE. 0h = High level 1h = Low level
6	AUX_SMPH_AUTOTAKE_DONE	R/W	0h	Select the event source level that sets EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE. 0h = High level 1h = Low level
5	AUX_TIMER1_EV	R/W	0h	Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER1_EV. 0h = High level 1h = Low level
4	AUX_TIMER0_EV	R/W	0h	Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER0_EV. 0h = High level 1h = Low level
3	AUX_TDC_DONE	R/W	0h	Select the event source level that sets EVTOMCUFLAGS.AUX_TDC_DONE. 0h = High level 1h = Low level
2	AUX_COMPB	R/W	0h	Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPB. 0h = Rising edge 1h = Falling edge
1	AUX_COMPA	R/W	0h	Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPA. 0h = Rising edge 1h = Falling edge
0	AUX_WU_EV	R/W	0h	Select the event source level that sets EVTOMCUFLAGS.AUX_WU_EV. 0h = High level 1h = Low level

20.8.3.14 EVTOMCUFLAGSCLR Register (Offset = 38h) [Reset = 00000000h]

EVTOMCUFLAGSCLR is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVTOMCUFLAGSCLR_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVTOMCUFLAGSCLR_TABLE.

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Events To MCU Flags Clear
Clear event flags in EVTOMCUFLAGS.
In order to clear a level sensitive event flag, the event must be deasserted.

Figure 20-79 EVTOMCUFLAGSCLR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
AUX_TIMER2_PULSE	AUX_TIMER2_EV3	AUX_TIMER2_EV2	AUX_TIMER2_EV1	AUX_TIMER2_EV0	AUX_ADC_IRQ	MCU_OBSMUX0	AUX_ADC_FIFO_ALMOST_FULL
W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h

7	6	5	4	3	2	1	0
AUX_ADC_DONE	AUX_SMPH_AUTOTAKE_DONE	AUX_TIMER1_EV	AUX_TIMER0_EV	AUX_TDC_DONE	AUX_COMPB	AUX_COMPA	AUX_WU_EV
W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h

Table 20-89 EVTOMCUFLAGSCLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	AUX_TIMER2_PULSE	W	0h	Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_PULSE. Read value is 0.
14	AUX_TIMER2_EV3	W	0h	Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV3. Read value is 0.
13	AUX_TIMER2_EV2	W	0h	Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV2. Read value is 0.
12	AUX_TIMER2_EV1	W	0h	Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV1. Read value is 0.
11	AUX_TIMER2_EV0	W	0h	Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV0. Read value is 0.
10	AUX_ADC_IRQ	W	0h	Write 1 to clear EVTOMCUFLAGS.AUX_ADC_IRQ. Read value is 0.
9	MCU_OBSMUX0	W	0h	Write 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0. Read value is 0.
8	AUX_ADC_FIFO_ALMOST_FULL	W	0h	Write 1 to clear EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL. Read value is 0.
7	AUX_ADC_DONE	W	0h	Write 1 to clear EVTOMCUFLAGS.AUX_ADC_DONE. Read value is 0.
6	AUX_SMPH_AUTOTAKE_DONE	W	0h	Write 1 to clear EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE. Read value is 0.
5	AUX_TIMER1_EV	W	0h	Write 1 to clear EVTOMCUFLAGS.AUX_TIMER1_EV. Read value is 0.
4	AUX_TIMER0_EV	W	0h	Write 1 to clear EVTOMCUFLAGS.AUX_TIMER0_EV. Read value is 0.
3	AUX_TDC_DONE	W	0h	Write 1 to clear EVTOMCUFLAGS.AUX_TDC_DONE. Read value is 0.
2	AUX_COMPB	W	0h	Write 1 to clear EVTOMCUFLAGS.AUX_COMPB. Read value is 0.
1	AUX_COMPA	W	0h	Write 1 to clear EVTOMCUFLAGS.AUX_COMPA. Read value is 0.
0	AUX_WU_EV	W	0h	Write 1 to clear EVTOMCUFLAGS.AUX_WU_EV. Read value is 0.

20.8.3.15 COMBEVTOMCUMASK Register (Offset = 3Ch) [Reset = 00000000h]

COMBEVTOMCUMASK is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_COMBEVTOMCUMASK_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_COMBEVTOMCUMASK_TABLE.

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Combined Event To MCU Mask
Select event flags in EVTOMCUFLAGS that contribute to the AUX_COMB event to EVENT and system CPU.
The AUX_COMB event is high as long as one or more of the included event flags are set.

Figure 20-80 COMBEVTOMCUMASK Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
AUX_TIMER2_PULSE	AUX_TIMER2_EV3	AUX_TIMER2_EV2	AUX_TIMER2_EV1	AUX_TIMER2_EV0	AUX_ADC_IRQ	MCU_OBSMUX0	AUX_ADC_FIFO_ALMOST_FULL
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
AUX_ADC_DONE	AUX_SMPH_AUTOTAKE_DONE	AUX_TIMER1_EV	AUX_TIMER0_EV	AUX_TDC_DONE	AUX_COMPB	AUX_COMPA	AUX_WU_EV
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 20-90 COMBEVTOMCUMASK Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	AUX_TIMER2_PULSE	R/W	0h	EVTOMCUFLAGS.AUX_TIMER2_PULSE contribution to the AUX_COMB event. 0: Exclude. 1: Include.
14	AUX_TIMER2_EV3	R/W	0h	EVTOMCUFLAGS.AUX_TIMER2_EV3 contribution to the AUX_COMB event. 0: Exclude. 1: Include.
13	AUX_TIMER2_EV2	R/W	0h	EVTOMCUFLAGS.AUX_TIMER2_EV2 contribution to the AUX_COMB event. 0: Exclude. 1: Include.
12	AUX_TIMER2_EV1	R/W	0h	EVTOMCUFLAGS.AUX_TIMER2_EV1 contribution to the AUX_COMB event. 0: Exclude. 1: Include.
11	AUX_TIMER2_EV0	R/W	0h	EVTOMCUFLAGS.AUX_TIMER2_EV0 contribution to the AUX_COMB event. 0: Exclude. 1: Include.
10	AUX_ADC_IRQ	R/W	0h	EVTOMCUFLAGS.AUX_ADC_IRQ contribution to the AUX_COMB event. 0: Exclude. 1: Include.
9	MCU_OBSMUX0	R/W	0h	EVTOMCUFLAGS.MCU_OBSMUX0 contribution to the AUX_COMB event. 0: Exclude. 1: Include.
8	AUX_ADC_FIFO_ALMOST_FULL	R/W	0h	EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL contribution to the AUX_COMB event. 0: Exclude. 1: Include.
7	AUX_ADC_DONE	R/W	0h	EVTOMCUFLAGS.AUX_ADC_DONE contribution to the AUX_COMB event. 0: Exclude. 1: Include.
6	AUX_SMPH_AUTOTAKE_DONE	R/W	0h	EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE contribution to the AUX_COMB event. 0: Exclude. 1: Include.
5	AUX_TIMER1_EV	R/W	0h	EVTOMCUFLAGS.AUX_TIMER1_EV contribution to the AUX_COMB event. 0: Exclude. 1: Include.
4	AUX_TIMER0_EV	R/W	0h	EVTOMCUFLAGS.AUX_TIMER0_EV contribution to the AUX_COMB event. 0: Exclude. 1: Include.
3	AUX_TDC_DONE	R/W	0h	EVTOMCUFLAGS.AUX_TDC_DONE contribution to the AUX_COMB event. 0: Exclude. 1: Include.
2	AUX_COMPB	R/W	0h	EVTOMCUFLAGS.AUX_COMPB contribution to the AUX_COMB event. 0: Exclude 1: Include.
1	AUX_COMPA	R/W	0h	EVTOMCUFLAGS.AUX_COMPA contribution to the AUX_COMB event. 0: Exclude. 1: Include.
0	AUX_WU_EV	R/W	0h	EVTOMCUFLAGS.AUX_WU_EV contribution to the AUX_COMB event. 0: Exclude. 1: Include.

20.8.3.16 EVOBSCFG Register (Offset = 40h) [Reset = 00000000h]

EVOBSCFG is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVOBSCFG_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVOBSCFG_TABLE.

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Event Observation Configuration

Figure 20-81 EVOBSCFG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED										EVOBS_SEL
R-0h										R/W-0h

Table 20-91 EVOBSCFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R	0h	Reserved
5-0	EVOBS_SEL	R/W	0h	Select which event from the asynchronous event bus that represents AUX_EV_OBS in AUX_AIODIOn. 0h = EVSTAT0.AUXIO0 1h = EVSTAT0.AUXIO1 2h = EVSTAT0.AUXIO2 3h = EVSTAT0.AUXIO3 4h = EVSTAT0.AUXIO4 5h = EVSTAT0.AUXIO5 6h = EVSTAT0.AUXIO6 7h = EVSTAT0.AUXIO7 8h = EVSTAT0.AUXIO8 9h = EVSTAT0.AUXIO9 Ah = EVSTAT0.AUXIO10 Bh = EVSTAT0.AUXIO11 Ch = EVSTAT0.AUXIO12 Dh = EVSTAT0.AUXIO13 Eh = EVSTAT0.AUXIO14 Fh = EVSTAT0.AUXIO15 10h = EVSTAT1.AUXIO16 11h = EVSTAT1.AUXIO17 12h = EVSTAT1.AUXIO18 13h = EVSTAT1.AUXIO19 14h = EVSTAT1.AUXIO20 15h = EVSTAT1.AUXIO21 16h = EVSTAT1.AUXIO22 17h = EVSTAT1.AUXIO23 18h = EVSTAT1.AUXIO24 19h = EVSTAT1.AUXIO25 1Ah = EVSTAT1.AUXIO26 1Bh = EVSTAT1.AUXIO27 1Ch = EVSTAT1.AUXIO28 1Dh = EVSTAT1.AUXIO29 1Eh = EVSTAT1.AUXIO30 1Fh = EVSTAT1.AUXIO31 20h = EVSTAT2.MANUAL_EV 21h = EVSTAT2.AON_RTC_CH2 22h = EVSTAT2.AON_RTC_CH2_DLY 23h = EVSTAT2.AON_RTC_4KHZ 24h = EVSTAT2.AON_BATMON_BAT_UPD 25h = EVSTAT2.AON_BATMON_TEMP_UPD 26h = EVSTAT2.SCLK_LF 27h = EVSTAT2.PWR_DWN 28h = EVSTAT2.MCU_ACTIVE 29h = EVSTAT2.VDDR_RECHARGE 2Ah = EVSTAT2.ACLK_REF 2Bh = EVSTAT2.MCU_EV 2Ch = EVSTAT2.MCU_OBSMUX0 2Dh = EVSTAT2.MCU_OBSMUX1 2Eh = EVSTAT2.AUX_COMPA 2Fh = EVSTAT2.AUX_COMPB 30h = EVSTAT3.AUX_TIMER2_EV0 31h = EVSTAT3.AUX_TIMER2_EV1 32h = EVSTAT3.AUX_TIMER2_EV2 33h = EVSTAT3.AUX_TIMER2_EV3 34h = EVSTAT3.AUX_TIMER2_PULSE 35h = EVSTAT3.AUX_TIMER1_EV 36h = EVSTAT3.AUX_TIMER0_EV 37h = EVSTAT3.AUX_TDC_DONE 38h = EVSTAT3.AUX_ISRC_RESET_N 39h = EVSTAT3.AUX_ADC_DONE 3Ah = EVSTAT3.AUX_ADC_IRQ 3Bh = EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL 3Ch = EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY 3Dh = EVSTAT3.AUX_SMPH_AUTOTAKE_DONE 3Eh = EVSTAT3.AUX_DAC_HOLD_ACTIVE 3Fh = EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY

Bit

Field

Type

Reset

Description

31-6

RESERVED

Reserved

5-0

EVOBS_SEL

R/W

Select which event from the asynchronous event bus that represents AUX_EV_OBS in AUX_AIODIOn.

0h = EVSTAT0.AUXIO0

1h = EVSTAT0.AUXIO1

2h = EVSTAT0.AUXIO2

3h = EVSTAT0.AUXIO3

4h = EVSTAT0.AUXIO4

5h = EVSTAT0.AUXIO5

6h = EVSTAT0.AUXIO6

7h = EVSTAT0.AUXIO7

8h = EVSTAT0.AUXIO8

9h = EVSTAT0.AUXIO9

Ah = EVSTAT0.AUXIO10

Bh = EVSTAT0.AUXIO11

Ch = EVSTAT0.AUXIO12

Dh = EVSTAT0.AUXIO13

Eh = EVSTAT0.AUXIO14

Fh = EVSTAT0.AUXIO15

10h = EVSTAT1.AUXIO16

11h = EVSTAT1.AUXIO17

12h = EVSTAT1.AUXIO18

13h = EVSTAT1.AUXIO19

14h = EVSTAT1.AUXIO20

15h = EVSTAT1.AUXIO21

16h = EVSTAT1.AUXIO22

17h = EVSTAT1.AUXIO23

18h = EVSTAT1.AUXIO24

19h = EVSTAT1.AUXIO25

1Ah = EVSTAT1.AUXIO26

1Bh = EVSTAT1.AUXIO27

1Ch = EVSTAT1.AUXIO28

1Dh = EVSTAT1.AUXIO29

1Eh = EVSTAT1.AUXIO30

1Fh = EVSTAT1.AUXIO31

20h = EVSTAT2.MANUAL_EV

21h = EVSTAT2.AON_RTC_CH2

22h = EVSTAT2.AON_RTC_CH2_DLY

23h = EVSTAT2.AON_RTC_4KHZ

24h = EVSTAT2.AON_BATMON_BAT_UPD

25h = EVSTAT2.AON_BATMON_TEMP_UPD

26h = EVSTAT2.SCLK_LF

27h = EVSTAT2.PWR_DWN

28h = EVSTAT2.MCU_ACTIVE

29h = EVSTAT2.VDDR_RECHARGE

2Ah = EVSTAT2.ACLK_REF

2Bh = EVSTAT2.MCU_EV

2Ch = EVSTAT2.MCU_OBSMUX0

2Dh = EVSTAT2.MCU_OBSMUX1

2Eh = EVSTAT2.AUX_COMPA

2Fh = EVSTAT2.AUX_COMPB

30h = EVSTAT3.AUX_TIMER2_EV0

31h = EVSTAT3.AUX_TIMER2_EV1

32h = EVSTAT3.AUX_TIMER2_EV2

33h = EVSTAT3.AUX_TIMER2_EV3

34h = EVSTAT3.AUX_TIMER2_PULSE

35h = EVSTAT3.AUX_TIMER1_EV

36h = EVSTAT3.AUX_TIMER0_EV

37h = EVSTAT3.AUX_TDC_DONE

38h = EVSTAT3.AUX_ISRC_RESET_N

39h = EVSTAT3.AUX_ADC_DONE

3Ah = EVSTAT3.AUX_ADC_IRQ

3Bh = EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL

3Ch = EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY

3Dh = EVSTAT3.AUX_SMPH_AUTOTAKE_DONE

3Eh = EVSTAT3.AUX_DAC_HOLD_ACTIVE

3Fh = EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY

20.8.3.17 PROGDLY Register (Offset = 44h) [Reset = 00000000h]

PROGDLY is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_PROGDLY_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_PROGDLY_TABLE.

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Programmable Delay

Figure 20-82 PROGDLY Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																VALUE
R-0h																R/W-0h

Table 20-92 PROGDLY Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	VALUE	R/W	0h	VALUE decrements to 0 at a rate of 1 MHz. The event AUX_PROG_DLY_IDLE is high when VALUE is 0, otherwise it is low. Only use the programmable delay counter and the AUX_PROG_DLY_IDLE event when AUX_SYSIF:OPMODEACK.ACK equals A or LP. Decrementation of VALUE halts when either is true: - AUX_SCE:CTL.DBG_FREEZE_EN is set and system CPU is halted in debug mode. - AUX_SYSIF:TIMERHALT.PROGDLY is set.

20.8.3.18 MANUAL Register (Offset = 48h) [Reset = 00000000h]

MANUAL is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_MANUAL_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_MANUAL_TABLE.

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Manual
Programmable event.

Figure 20-83 MANUAL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															EV
R-0h															R/W-0h

Table 20-93 MANUAL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	EV	R/W	0h	This bit field sets the value of EVSTAT2.MANUAL_EV.

20.8.3.19 EVSTAT0L Register (Offset = 4Ch) [Reset = 00000000h]

EVSTAT0L is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT0L_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT0L_TABLE.

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Event Status 0 Low

Figure 20-84 EVSTAT0L Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								ALIAS_EV
R-0h																								R-0h

Table 20-94 EVSTAT0L Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	ALIAS_EV	R	0h	Alias of EVSTAT0 event 7 down to 0.

20.8.3.20 EVSTAT0H Register (Offset = 50h) [Reset = 00000000h]

EVSTAT0H is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT0H_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT0H_TABLE.

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Event Status 0 High

Figure 20-85 EVSTAT0H Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								ALIAS_EV
R-0h																								R-0h

Table 20-95 EVSTAT0H Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	ALIAS_EV	R	0h	Alias of EVSTAT0 event 15 down to 8.

20.8.3.21 EVSTAT1L Register (Offset = 54h) [Reset = 00000000h]

EVSTAT1L is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT1L_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT1L_TABLE.

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Event Status 1 Low

Figure 20-86 EVSTAT1L Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								ALIAS_EV
R-0h																								R-0h

Table 20-96 EVSTAT1L Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	ALIAS_EV	R	0h	Alias of EVSTAT1 event 7 down to 0.

20.8.3.22 EVSTAT1H Register (Offset = 58h) [Reset = 00000000h]

EVSTAT1H is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT1H_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT1H_TABLE.

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Event Status 1 High

Figure 20-87 EVSTAT1H Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								ALIAS_EV
R-0h																								R-0h

Table 20-97 EVSTAT1H Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	ALIAS_EV	R	0h	Alias of EVSTAT1 event 15 down to 8.

20.8.3.23 EVSTAT2L Register (Offset = 5Ch) [Reset = 00000000h]

EVSTAT2L is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT2L_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT2L_TABLE.

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Event Status 2 Low

Figure 20-88 EVSTAT2L Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								ALIAS_EV
R-0h																								R-0h

Table 20-98 EVSTAT2L Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	ALIAS_EV	R	0h	Alias of EVSTAT2 event 7 down to 0.

20.8.3.24 EVSTAT2H Register (Offset = 60h) [Reset = 00000000h]

EVSTAT2H is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT2H_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT2H_TABLE.

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Event Status 2 High

Figure 20-89 EVSTAT2H Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								ALIAS_EV
R-0h																								R-0h

Table 20-99 EVSTAT2H Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	ALIAS_EV	R	0h	Alias of EVSTAT2 event 15 down to 8.

20.8.3.25 EVSTAT3L Register (Offset = 64h) [Reset = 00000000h]

EVSTAT3L is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT3L_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT3L_TABLE.

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Event Status 3 Low

Figure 20-90 EVSTAT3L Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								ALIAS_EV
R-0h																								R-0h

Table 20-100 EVSTAT3L Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	ALIAS_EV	R	0h	Alias of EVSTAT3 event 7 down to 0.

20.8.3.26 EVSTAT3H Register (Offset = 68h) [Reset = 00000000h]

EVSTAT3H is shown in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT3H_FIGURE and described in #AUX_EVCTL_AUX_EVCTL_MMAP_AUX_EVCTL_AUX_EVCTL_ALL_EVSTAT3H_TABLE.

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Event Status 3 High

Figure 20-91 EVSTAT3H Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								ALIAS_EV
R-0h																								R-0h

Table 20-101 EVSTAT3H Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	ALIAS_EV	R	0h	Alias of EVSTAT3 event 15 down to 8.