SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
#ADI_4_AUX_ADI_4_AUX_MMAP1_TABLE_1 lists the memory-mapped registers for the AUX_ADI4 registers. All register offset addresses not listed in #ADI_4_AUX_ADI_4_AUX_MMAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0h | MUX0 | Internal | #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_MUX0 |
| 1h | MUX1 | Internal | #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_MUX1 |
| 2h | MUX2 | Internal | #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_MUX2 |
| 3h | MUX3 | Internal | #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_MUX3 |
| 4h | ISRC | Current Source | #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_ISRC |
| 5h | COMP | Comparator | #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_COMP |
| 7h | MUX4 | Internal | #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_MUX4 |
| 8h | ADC0 | ADC Control 0 | #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_ADC0 |
| 9h | ADC1 | ADC Control 1 | #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_ADC1 |
| Ah | ADCREF0 | ADC Reference 0 | #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_ADCREF0 |
| Bh | ADCREF1 | ADC Reference 1 | #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_ADCREF1 |
| Eh | LPMBIAS | Internal | #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_LPMBIAS |
Complex bit access types are encoded to fit into small table cells. #ADI_4_AUX_ADI_4_AUX_MMAP1_LEGEND shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
MUX0 is shown in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_MUX0_FIGURE and described in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_MUX0_TABLE.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ADCCOMPB_IN | RESERVED | COMPA_REF | ||||
| R-0h | R/W-0h | R-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R | 0h | Reserved |
| 6 | ADCCOMPB_IN | R/W | 0h | Internal. Only to be used through TI provided API. |
| 5-4 | RESERVED | R | 0h | Reserved |
| 3-0 | COMPA_REF | R/W | 0h | Internal. Only to be used through TI provided API. |
MUX1 is shown in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_MUX1_FIGURE and described in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_MUX1_TABLE.
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Internal. Only to be used through TI provided API.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COMPA_IN | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | COMPA_IN | R/W | 0h | Internal. Only to be used through TI provided API. |
MUX2 is shown in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_MUX2_FIGURE and described in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_MUX2_TABLE.
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Internal. Only to be used through TI provided API.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADCCOMPB_IN | DAC_VREF_SEL | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-3 | ADCCOMPB_IN | R/W | 0h | Internal. Only to be used through TI provided API. |
| 2-0 | DAC_VREF_SEL | R/W | 0h | Internal. Only to be used through TI provided API. |
MUX3 is shown in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_MUX3_FIGURE and described in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_MUX3_TABLE.
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Internal. Only to be used through TI provided API.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADCCOMPB_IN | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | ADCCOMPB_IN | R/W | 0h | Internal. Only to be used through TI provided API. |
ISRC is shown in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_ISRC_FIGURE and described in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_ISRC_TABLE.
Return to the Summary Table.
Current Source
Strength and trim control for current source. Only to be used through TI provided API.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TRIM | RESERVED | EN | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-2 | TRIM | R/W | 0h | Adjust current from current source. Output currents may be combined to get desired total current. 0h = No current connected 1h = 0P25U : 0.25 uA 2h = 0P5U : 0.5 uA 4h = 1P0U : 1.0 uA 8h = 2P0U : 2.0 uA 10h = 4P5U : 4.5 uA 20h = 11P75U : 11.75 uA |
| 1 | RESERVED | R | 0h | Reserved |
| 0 | EN | R/W | 0h | Current source enable |
COMP is shown in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_COMP_FIGURE and described in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_COMP_TABLE.
Return to the Summary Table.
Comparator
Control COMPA and COMPB comparators. Only to be used through TI provided API.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COMPA_REF_RES_EN | COMPA_REF_CURR_EN | LPM_BIAS_WIDTH_TRIM | COMPB_EN | RESERVED | COMPA_EN | ||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | COMPA_REF_RES_EN | R/W | 0h | Enables 400kΩ resistance from COMPA reference node to ground. Used with COMPA_REF_CURR_EN to generate voltage reference for cap-sense. |
| 6 | COMPA_REF_CURR_EN | R/W | 0h | Enables 2uA IPTAT current from ISRC to COMPA reference node. Requires ISRC.EN = 1. Used with COMPA_REF_RES_EN to generate voltage reference for cap-sense. |
| 5-3 | LPM_BIAS_WIDTH_TRIM | R/W | 0h | Internal. Only to be used through TI provided API. |
| 2 | COMPB_EN | R/W | 0h | COMPB enable |
| 1 | RESERVED | R | 0h | Reserved |
| 0 | COMPA_EN | R/W | 0h | COMPA enable |
MUX4 is shown in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_MUX4_FIGURE and described in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_MUX4_TABLE.
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Internal. Only to be used through TI provided API.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COMPA_REF | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | COMPA_REF | R/W | 0h | Internal. Only to be used through TI provided API. |
ADC0 is shown in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_ADC0_FIGURE and described in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_ADC0_TABLE.
Return to the Summary Table.
ADC Control 0
ADC Sample Control. Only to be used through TI provided API.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SMPL_MODE | SMPL_CYCLE_EXP | RESERVED | RESET_N | EN | |||
| R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | SMPL_MODE | R/W | 0h | ADC Sampling mode: 0: Synchronous mode 1: Asynchronous mode The ADC does a sample-and-hold before conversion. In synchronous mode the sampling starts when the ADC clock detects a rising edge on the trigger signal. Jitter/uncertainty will be inferred in the detection if the trigger signal originates from a domain that is asynchronous to the ADC clock. SMPL_CYCLE_EXP determines the the duration of sampling. Conversion starts immediately after sampling ends. In asynchronous mode the sampling is continuous when enabled. Sampling ends and conversion starts immediately with the rising edge of the trigger signal. Sampling restarts when the conversion has finished. Asynchronous mode is useful when it is important to avoid jitter in the sampling instant of an externally driven signal |
| 6-3 | SMPL_CYCLE_EXP | R/W | 0h | Controls the sampling duration before conversion when the ADC is operated in synchronous mode (SMPL_MODE = 0). The setting has no effect in asynchronous mode. The sampling duration is given as 2SMPL_CYCLE_EXP + 1 / 6 us.
3h = 2P7_US : 16x 6 MHz clock periods = 2.7us 4h = 5P3_US : 32x 6 MHz clock periods = 5.3us 5h = 10P6_US : 64x 6 MHz clock periods = 10.6us 6h = 21P3_US : 128x 6 MHz clock periods = 21.3us 7h = 42P6_US : 256x 6 MHz clock periods = 42.6us 8h = 85P3_US : 512x 6 MHz clock periods = 85.3us 9h = 170_US : 1024x 6 MHz clock periods = 170us Ah = 341_US : 2048x 6 MHz clock periods = 341us Bh = 682_US : 4096x 6 MHz clock periods = 682us Ch = 1P37_MS : 8192x 6 MHz clock periods = 1.37ms Dh = 2P73_MS : 16384x 6 MHz clock periods = 2.73ms Eh = 5P46_MS : 32768x 6 MHz clock periods = 5.46ms Fh = 10P9_MS : 65536x 6 MHz clock periods = 10.9ms |
| 2 | RESERVED | R | 0h | Reserved |
| 1 | RESET_N | R/W | 0h | Reset ADC digital subchip, active low. ADC must be reset every time it is reconfigured. 0: Reset 1: Normal operation |
| 0 | EN | R/W | 0h | ADC Enable 0: Disable 1: Enable |
ADC1 is shown in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_ADC1_FIGURE and described in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_ADC1_TABLE.
Return to the Summary Table.
ADC Control 1
ADC Comparator Control. Only to be used through TI provided API.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SCALE_DIS | ||||||
| R-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-1 | RESERVED | R | 0h | Reserved |
| 0 | SCALE_DIS | R/W | 0h | Internal. Only to be used through TI provided API. |
ADCREF0 is shown in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_ADCREF0_FIGURE and described in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_ADCREF0_TABLE.
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ADC Reference 0
Control reference used by the ADC. Only to be used through TI provided API.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | REF_ON_IDLE | IOMUX | EXT | SRC | RESERVED | EN | |
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R | 0h | Reserved |
| 6 | REF_ON_IDLE | R/W | 0h | Enable ADCREF in IDLE state. 0: Disabled in IDLE state 1: Enabled in IDLE state Keep ADCREF enabled when ADC0.SMPL_MODE = 0. Recommendation: Enable ADCREF always when ADC0.SMPL_CYCLE_EXP is less than 0x6 (21.3us sampling time). |
| 5 | IOMUX | R/W | 0h | Internal. Only to be used through TI provided API. |
| 4 | EXT | R/W | 0h | Internal. Only to be used through TI provided API. |
| 3 | SRC | R/W | 0h | ADC reference source: 0: Fixed reference = 4.3V 1: Relative reference = VDDS |
| 2-1 | RESERVED | R | 0h | Reserved |
| 0 | EN | R/W | 0h | ADC reference module enable: 0: ADC reference module powered down 1: ADC reference module enabled |
ADCREF1 is shown in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_ADCREF1_FIGURE and described in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_ADCREF1_TABLE.
Return to the Summary Table.
ADC Reference 1
Control reference used by the ADC. Only to be used through TI provided API.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VTRIM | ||||||
| R-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R | 0h | Reserved |
| 5-0 | VTRIM | R/W | 0h | Trim output voltage of ADC fixed reference (64 steps, 2's complement). Applies only for ADCREF0.SRC = 0. Examples: 0x00 - nominal voltage 1.43V 0x01 - nominal + 0.4% 1.435V 0x3F - nominal - 0.4% 1.425V 0x1F - maximum voltage 1.6V 0x20 - minimum voltage 1.3V |
LPMBIAS is shown in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_LPMBIAS_FIGURE and described in #ADI_4_AUX_ADI_4_AUX_MMAP1_ADI_4_AUX_ALL_LPMBIAS_TABLE.
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Internal. Only to be used through TI provided API.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LPM_TRIM_IOUT | ||||||
| R-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R | 0h | Reserved |
| 5-0 | LPM_TRIM_IOUT | R/W | 0h | Internal. Only to be used through TI provided API. |