SPRUJB3 User guide | 德州仪器 TI.com.cn

SPRUJB3C March 2024 – November 2025 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1

4.14.2.3 RTI_CFG1 Integration

Table 4-377 RTI_CFG1 Module Allocations

Instance	MAIN	MCU	WKUP
RTI4	✓
RTI5	✓
RTI15	✓
RTI0	✓
RTI1	✓
RTI2	✓
RTI3	✓
RTI8	✓
MCU_RTI0		✓
WKUP_RTI0			✓

Table 4-378 Integration Attributes for RTI_CFG1

Module Instance	Power Sleep Controller	Power Domain	Module Domain	Index	Default	Controllable	Dependencies
RTI4	PSC0	PD_C7DSP0	LPSC_main_c7dsp0_core	67	OFF	YES	LPSC_main_c7dsp0_common
RTI5	PSC0	PD_C7DSP1	LPSC_main_c7dsp1_core	76	OFF	YES	LPSC_main_c7dsp1_common
RTI15	PSC0	PD_GPU_CTRL	LPSC_main_gpu_ctrl	60	OFF	YES	LPSC_main_ip
RTI0	PSC0	PD_MPU_CLST0_CORE0	LPSC_main_mpu_clst0_core0	56	OFF	YES	LPSC_main_mpu_clst0
RTI1	PSC0	PD_MPU_CLST0_CORE1	LPSC_main_mpu_clst0_core1	57	OFF	YES	LPSC_main_mpu_clst0
RTI2	PSC0	PD_MPU_CLST0_CORE2	LPSC_main_mpu_clst0_core2	58	OFF	YES	LPSC_main_mpu_clst0
RTI3	PSC0	PD_MPU_CLST0_CORE3	LPSC_main_mpu_clst0_core3	59	OFF	YES	LPSC_main_mpu_clst0
RTI8	PSC0	PD_MAIN_MCUSS0	LPSC_main_mcuss0_core0	79	OFF	YES	LPSC_main_ip
MCU_RTI0	WKUP_PSC0	PD_MCUSS	LPSC_mcu_r5	6	OFF	YES	LPSC_MCU_common
WKUP_RTI0	PSC0	GP_CORE	LPSC_main_dm	1	OFF	YES	LPSC_main_alwayson

Table 4-379 Clock Integration for RTI_CFG1

Module Instance	Module Clock Input	Source Clock	Source Control Register	Description
RTI4	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD4_CLKSEL[1:0]=0	functional clock
RTI4	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD4_CLKSEL[1:0]=0	functional clock
RTI4	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD4_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
RTI4	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD4_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
RTI4	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD4_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
RTI4	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD4_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
RTI4	FCLK	LFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD4_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
RTI4	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD4_CLKSEL[1:0]=2	functional clock
RTI4	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD4_CLKSEL[1:0]=3	functional clock
RTI4	ICLK	MAIN_SYSCLK0/4		interface clock
RTI5	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD5_CLKSEL[1:0]=0	functional clock
RTI5	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD5_CLKSEL[1:0]=0	functional clock
RTI5	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD5_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
RTI5	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD5_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
RTI5	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD5_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
RTI5	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD5_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
RTI5	FCLK	LFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD5_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
RTI5	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD5_CLKSEL[1:0]=2	functional clock
RTI5	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD5_CLKSEL[1:0]=3	functional clock
RTI5	ICLK	MAIN_SYSCLK0/4		interface clock
RTI15	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD15_CLKSEL[1:0]=0	functional clock
RTI15	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD15_CLKSEL[1:0]=0	functional clock
RTI15	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD15_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
RTI15	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD15_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
RTI15	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD15_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
RTI15	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD15_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
RTI15	FCLK	LFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD15_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
RTI15	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD15_CLKSEL[1:0]=2	functional clock
RTI15	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD15_CLKSEL[1:0]=3	functional clock
RTI15	ICLK	MAIN_SYSCLK0/4		interface clock
RTI0	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD0_CLKSEL[1:0]=0	functional clock
RTI0	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD0_CLKSEL[1:0]=0	functional clock
RTI0	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD0_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
RTI0	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD0_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
RTI0	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD0_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
RTI0	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD0_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
RTI0	FCLK	LFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD0_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
RTI0	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD0_CLKSEL[1:0]=2	functional clock
RTI0	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD0_CLKSEL[1:0]=3	functional clock
RTI0	ICLK	MAIN_SYSCLK0/4		interface clock
RTI1	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD1_CLKSEL[1:0]=0	functional clock
RTI1	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD1_CLKSEL[1:0]=0	functional clock
RTI1	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD1_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
RTI1	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD1_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
RTI1	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD1_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
RTI1	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD1_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
RTI1	FCLK	LFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD1_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
RTI1	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD1_CLKSEL[1:0]=2	functional clock
RTI1	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD1_CLKSEL[1:0]=3	functional clock
RTI1	ICLK	MAIN_SYSCLK0/4		interface clock
RTI2	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD2_CLKSEL[1:0]=0	functional clock
RTI2	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD2_CLKSEL[1:0]=0	functional clock
RTI2	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD2_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
RTI2	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD2_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
RTI2	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD2_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
RTI2	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD2_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
RTI2	FCLK	LFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD2_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
RTI2	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD2_CLKSEL[1:0]=2	functional clock
RTI2	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD2_CLKSEL[1:0]=3	functional clock
RTI2	ICLK	MAIN_SYSCLK0/4		interface clock
RTI3	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD3_CLKSEL[1:0]=0	functional clock
RTI3	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD3_CLKSEL[1:0]=0	functional clock
RTI3	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD3_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
RTI3	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD3_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
RTI3	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD3_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
RTI3	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD3_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
RTI3	FCLK	LFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD3_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
RTI3	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD3_CLKSEL[1:0]=2	functional clock
RTI3	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD3_CLKSEL[1:0]=3	functional clock
RTI3	ICLK	MAIN_SYSCLK0/4		interface clock
RTI8	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD8_CLKSEL[1:0]=0	functional clock
RTI8	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD8_CLKSEL[1:0]=0	functional clock
RTI8	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD8_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
RTI8	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD8_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
RTI8	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD8_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
RTI8	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD8_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
RTI8	FCLK	LFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_WWD8_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
RTI8	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_WWD8_CLKSEL[1:0]=2	functional clock
RTI8	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_WWD8_CLKSEL[1:0]=3	functional clock
RTI8	ICLK	MAIN_SYSCLK0/4		interface clock
MCU_RTI0	FCLK	CLK_12M_RC	MCU_CTRL_MMR_CFG0_MCU_WWD0_CLKSEL[1:0]=0	functional clock
MCU_RTI0	FCLK	HFOSC0 (INSTANCE)	MCU_CTRL_MMR_CFG0_MCU_WWD0_CLKSEL[1:0]=0	functional clock
MCU_RTI0	FCLK	CLK_32K_RC	MCU_CTRL_MMR_CFG0_MCU_WWD0_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
MCU_RTI0	FCLK	CLK_12M_RC	MCU_CTRL_MMR_CFG0_MCU_WWD0_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
MCU_RTI0	FCLK	HFOSC0 (INSTANCE)	MCU_CTRL_MMR_CFG0_MCU_WWD0_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
MCU_RTI0	FCLK	CLK_32K_RC	MCU_CTRL_MMR_CFG0_MCU_WWD0_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
MCU_RTI0	FCLK	LFOSC0 (INSTANCE)	MCU_CTRL_MMR_CFG0_MCU_WWD0_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
MCU_RTI0	FCLK	CLK_12M_RC	MCU_CTRL_MMR_CFG0_MCU_WWD0_CLKSEL[1:0]=2	functional clock
MCU_RTI0	FCLK	CLK_32K_RC	MCU_CTRL_MMR_CFG0_MCU_WWD0_CLKSEL[1:0]=3	functional clock
MCU_RTI0	ICLK	MCU_SYSCLK0/4		interface clock
WKUP_RTI0	FCLK	CLK_12M_RC	WKUP_CTRL_MMR_CFG0_WKUP_WWD0_CLKSEL[1:0]=0	functional clock
WKUP_RTI0	FCLK	HFOSC0 (INSTANCE)	WKUP_CTRL_MMR_CFG0_WKUP_WWD0_CLKSEL[1:0]=0	functional clock
WKUP_RTI0	FCLK	CLK_32K_RC	WKUP_CTRL_MMR_CFG0_WKUP_WWD0_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
WKUP_RTI0	FCLK	CLK_12M_RC	WKUP_CTRL_MMR_CFG0_WKUP_WWD0_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
WKUP_RTI0	FCLK	HFOSC0 (INSTANCE)	WKUP_CTRL_MMR_CFG0_WKUP_WWD0_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
WKUP_RTI0	FCLK	CLK_32K_RC	WKUP_CTRL_MMR_CFG0_WKUP_WWD0_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
WKUP_RTI0	FCLK	LFOSC0 (INSTANCE)	WKUP_CTRL_MMR_CFG0_WKUP_WWD0_CLKSEL[1:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
WKUP_RTI0	FCLK	CLK_12M_RC	WKUP_CTRL_MMR_CFG0_WKUP_WWD0_CLKSEL[1:0]=2	functional clock
WKUP_RTI0	FCLK	CLK_32K_RC	WKUP_CTRL_MMR_CFG0_WKUP_WWD0_CLKSEL[1:0]=3	functional clock
WKUP_RTI0	ICLK	DM_CLK/4		interface clock

Table 4-380 Reset Integration for RTI_CFG1

Module Instance	Source	Description
RTI4	PSC0	RTI4 reset
RTI5	PSC0	RTI5 reset
RTI15	PSC0	RTI15 reset
RTI0	PSC0	RTI0 reset
RTI1	PSC0	RTI1 reset
RTI2	PSC0	RTI2 reset
RTI3	PSC0	RTI3 reset
RTI8	PSC0	RTI8 reset
MCU_RTI0	WKUP_PSC0	MCU_RTI0 reset
WKUP_RTI0	PSC0	WKUP_RTI0 reset

Table 4-381 Hardware Requests for RTI_CFG1

Module Instance	Module Interrupt Signal	Destination Interrupt Input	Destination	Description	Type
RTI4	RTI4_intr_wwd_0	ESM0_esm_pls_event0_236	ESM0	RTI4 interrupt request	pulse
RTI4	RTI4_intr_wwd_0	ESM0_esm_pls_event1_236	ESM0	RTI4 interrupt request	pulse
RTI4	RTI4_intr_wwd_0	ESM0_esm_pls_event2_236	ESM0	RTI4 interrupt request	pulse
RTI4	RTI4_intr_wwd_0	C7X256V0_CLEC_soc_events_in_4	C7X256V0_CLEC	RTI4 interrupt request	pulse
RTI5	RTI5_intr_wwd_0	ESM0_esm_pls_event0_239	ESM0	RTI5 interrupt request	pulse
RTI5	RTI5_intr_wwd_0	ESM0_esm_pls_event1_239	ESM0	RTI5 interrupt request	pulse
RTI5	RTI5_intr_wwd_0	ESM0_esm_pls_event2_239	ESM0	RTI5 interrupt request	pulse
RTI5	RTI5_intr_wwd_0	C7X256V1_CLEC_soc_events_in_4	C7X256V1_CLEC	RTI5 interrupt request	pulse
RTI15	RTI15_intr_wwd_0	ESM0_esm_pls_event0_248	ESM0	RTI15 interrupt request	pulse
RTI15	RTI15_intr_wwd_0	ESM0_esm_pls_event1_248	ESM0	RTI15 interrupt request	pulse
RTI15	RTI15_intr_wwd_0	ESM0_esm_pls_event2_248	ESM0	RTI15 interrupt request	pulse
RTI15	RTI15_intr_wwd_0	GICSS0_spi_207	GICSS0	RTI15 interrupt request	pulse
RTI15	RTI15_intr_wwd_0	C7X256V0_CLEC_gic_spi_207	C7X256V0_CLEC	RTI15 interrupt request	pulse
RTI15	RTI15_intr_wwd_0	C7X256V1_CLEC_gic_spi_207	C7X256V1_CLEC	RTI15 interrupt request	pulse
RTI0	RTI0_intr_wwd_0	ESM0_esm_pls_event0_224	ESM0	RTI0 interrupt request	pulse
RTI0	RTI0_intr_wwd_0	ESM0_esm_pls_event1_224	ESM0	RTI0 interrupt request	pulse
RTI0	RTI0_intr_wwd_0	ESM0_esm_pls_event2_224	ESM0	RTI0 interrupt request	pulse
RTI0	RTI0_intr_wwd_0	GICSS0_spi_252	GICSS0	RTI0 interrupt request	pulse
RTI0	RTI0_intr_wwd_0	C7X256V0_CLEC_gic_spi_252	C7X256V0_CLEC	RTI0 interrupt request	pulse
RTI0	RTI0_intr_wwd_0	C7X256V1_CLEC_gic_spi_252	C7X256V1_CLEC	RTI0 interrupt request	pulse
RTI1	RTI1_intr_wwd_0	ESM0_esm_pls_event0_225	ESM0	RTI1 interrupt request	pulse
RTI1	RTI1_intr_wwd_0	ESM0_esm_pls_event1_225	ESM0	RTI1 interrupt request	pulse
RTI1	RTI1_intr_wwd_0	ESM0_esm_pls_event2_225	ESM0	RTI1 interrupt request	pulse
RTI1	RTI1_intr_wwd_0	GICSS0_spi_253	GICSS0	RTI1 interrupt request	pulse
RTI1	RTI1_intr_wwd_0	C7X256V0_CLEC_gic_spi_253	C7X256V0_CLEC	RTI1 interrupt request	pulse
RTI1	RTI1_intr_wwd_0	C7X256V1_CLEC_gic_spi_253	C7X256V1_CLEC	RTI1 interrupt request	pulse
RTI2	RTI2_intr_wwd_0	ESM0_esm_pls_event0_241	ESM0	RTI2 interrupt request	pulse
RTI2	RTI2_intr_wwd_0	ESM0_esm_pls_event1_241	ESM0	RTI2 interrupt request	pulse
RTI2	RTI2_intr_wwd_0	ESM0_esm_pls_event2_241	ESM0	RTI2 interrupt request	pulse
RTI2	RTI2_intr_wwd_0	GICSS0_spi_254	GICSS0	RTI2 interrupt request	pulse
RTI2	RTI2_intr_wwd_0	C7X256V0_CLEC_gic_spi_254	C7X256V0_CLEC	RTI2 interrupt request	pulse
RTI2	RTI2_intr_wwd_0	C7X256V1_CLEC_gic_spi_254	C7X256V1_CLEC	RTI2 interrupt request	pulse
RTI3	RTI3_intr_wwd_0	ESM0_esm_pls_event0_242	ESM0	RTI3 interrupt request	pulse
RTI3	RTI3_intr_wwd_0	ESM0_esm_pls_event1_242	ESM0	RTI3 interrupt request	pulse
RTI3	RTI3_intr_wwd_0	ESM0_esm_pls_event2_242	ESM0	RTI3 interrupt request	pulse
RTI3	RTI3_intr_wwd_0	GICSS0_spi_255	GICSS0	RTI3 interrupt request	pulse
RTI3	RTI3_intr_wwd_0	C7X256V0_CLEC_gic_spi_255	C7X256V0_CLEC	RTI3 interrupt request	pulse
RTI3	RTI3_intr_wwd_0	C7X256V1_CLEC_gic_spi_255	C7X256V1_CLEC	RTI3 interrupt request	pulse
RTI8	RTI8_intr_wwd_0	ESM0_esm_pls_event0_249	ESM0	RTI8 interrupt request	pulse
RTI8	RTI8_intr_wwd_0	ESM0_esm_pls_event1_249	ESM0	RTI8 interrupt request	pulse
RTI8	RTI8_intr_wwd_0	ESM0_esm_pls_event2_249	ESM0	RTI8 interrupt request	pulse
RTI8	RTI8_intr_wwd_0	R5FSS0_CORE0_intr_30	R5FSS0_CORE0	RTI8 interrupt request	pulse
MCU_RTI0	MCU_RTI0_intr_wwd_0	WKUP_ESM0_esm_pls_event0_85	WKUP_ESM0	MCU_RTI0 interrupt request	pulse
MCU_RTI0	MCU_RTI0_intr_wwd_0	WKUP_ESM0_esm_pls_event1_85	WKUP_ESM0	MCU_RTI0 interrupt request	pulse
MCU_RTI0	MCU_RTI0_intr_wwd_0	WKUP_ESM0_esm_pls_event2_85	WKUP_ESM0	MCU_RTI0 interrupt request	pulse
MCU_RTI0	MCU_RTI0_intr_wwd_0	MCU_R5FSS0_CORE0_cpu0_intr_30	MCU_R5FSS0_CORE0	MCU_RTI0 interrupt request	pulse
WKUP_RTI0	WKUP_RTI0_intr_wwd_0	WKUP_ESM0_esm_pls_event0_86	WKUP_ESM0	WKUP_RTI0 interrupt request	pulse
WKUP_RTI0	WKUP_RTI0_intr_wwd_0	WKUP_ESM0_esm_pls_event1_86	WKUP_ESM0	WKUP_RTI0 interrupt request	pulse
WKUP_RTI0	WKUP_RTI0_intr_wwd_0	WKUP_ESM0_esm_pls_event2_86	WKUP_ESM0	WKUP_RTI0 interrupt request	pulse
WKUP_RTI0	WKUP_RTI0_intr_wwd_0	ESM0_esm_pls_event0_227	ESM0	WKUP_RTI0 interrupt request	pulse
WKUP_RTI0	WKUP_RTI0_intr_wwd_0	ESM0_esm_pls_event1_227	ESM0	WKUP_RTI0 interrupt request	pulse
WKUP_RTI0	WKUP_RTI0_intr_wwd_0	ESM0_esm_pls_event2_227	ESM0	WKUP_RTI0 interrupt request	pulse
WKUP_RTI0	WKUP_RTI0_intr_wwd_0	WKUP_R5FSS0_CORE0_intr_30	WKUP_R5FSS0_CORE0	WKUP_RTI0 interrupt request	pulse