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SPRUJB3C March 2024 – November 2025 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1

12.9.1.4.1.10.7 DISPC VP Timing Generator and Display Panel Settings

Each video port output has a dedicated timing generator supporting progressive and interlaced mode. It is clocked using the pixel clock and is configured to generate the video data and sync signals to match the desired video display standard timings.

Two-level configuration for enabling the video ports exists:

Via the individual DSS_VP1_CONTROL[0] ENABLE register bit for each VP. It allows each VP to be independently controlled by two different hosts.
Via the common DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE[2-0] VP_ENABLE register field. It allows two or more VP timing generators to be in sync by enabling them simultaneously with a single register write.

Both ENABLE and VP_ENABLE register fields must be set in order for a VP (timing generator) to start.

Figure 12-562 shows the timing generator display parameters.

Figure 12-562 DISPC VP Display Timing Parameters

The width of VP output data bus is configured in the DSS_VP1_CONTROL[10-8] DATALINES register field, when TDM feature is disabled. When TDM is enabled, the width of the output data bus is defined according to Section 12.9.1.4.1.10.6, DISPC VP Multiple Cycle Output Format (TDM).

The size of the display panel is defined by:

Number of lines per frame, DSS_VP1_SIZE_SCREEN[27-16] LPP bit field, with a value from 1 to 4096
Number of pixels per line, DSS_VP1_SIZE_SCREEN[11-0] PPL bit field, with a value from 1 to 4096

Standard HSYNC/VSYNC timing generation is programmable as follows:

Horizontal front porch is set in the DSS_VP1_TIMING_H[19-8] HFP bit field.
Horizontal back porch is set in the DSS_VP1_TIMING_H[31-20] HBP bit field.
Horizontal synchronization pulse width is set in the DSS_VP1_TIMING_H[7-0] HSW bit field.
Vertical front porch is set in the DSS_VP1_TIMING_V[19-8] VFP bit field.
Vertical back porch is set in the DSS_VP1_TIMING_V[31-20] VBP bit field.
Vertical synchronization pulse width is set in the DSS_VP1_TIMING_V[7-0] VSW bit field.

When the output is in BT.1120 or BT.656 mode, the following timing constants are mapped onto the DSS_VP1_TIMING_H and DSS_VP1_TIMING_V registers:

Progressive mode:
- Horizontal blanking (12 bits) is set in the {DSS_VP1_TIMING_V[3-0] VSW, DSS_VP1_TIMING_H[7-0] HSW} register fields (up to 2048 bytes of horizontal blanking supported).
- Vertical frame blanking No 1 is set in the DSS_VP1_TIMING_V[19-8] VFP bit field.
- Vertical frame blanking No 2 is set in the DSS_VP1_TIMING_V[31-20] VBP bit field.
- Number of lines per frame is set in the DSS_VP1_SIZE_SCREEN[27-16] LPP bit field.
- Number of pixels per line is set in the DSS_VP1_SIZE_SCREEN[11-0] PPL bit field.
Interlaced mode:
- Horizontal blanking (12 bits) is set in the {DSS_VP1_TIMING_V[3-0] VSW, DSS_VP1_TIMING_H[7-0] HSW} register fields (up to 2048 bytes of horizontal blanking supported).
- Vertical field blanking No.1 for Even Field is set in the DSS_VP1_TIMING_H[19-8] HFP bit field.
- Vertical field blanking No.2 for Even Field is set in the DSS_VP1_TIMING_H[31-20] HBP bit field.
- Vertical field blanking No.1 for Odd Field is set in the DSS_VP1_TIMING_V[19-8] VFP bit field.
- Vertical field blanking No.2 for Odd Field is set in the DSS_VP1_TIMING_V[31-20] VBP bit field.
- Number of lines per field (even) is set in the DSS_VP1_SIZE_SCREEN[27-16] LPP bit field.
- Delta number of odd field compared to even field (in a single line) is set in the DSS_VP1_SIZE_SCREEN[15-14] DELTA_LPP bit field. The DELTA_LPP field only controls the output channel and not the size of the field fetched from the frame buffer in memory. This field must be set to zero for YUV420 format.
- Number of pixels per line is set in the DSS_VP1_SIZE_SCREEN[11-0] PPL bit field.

Horizontal/vertical synchronization and output enable signals polarity are programmable by setting the DSS_VP1_POL_FREQ[12] IVS, [13] IHS, and [15] IEO register bits. These signals can be gated by setting the DSS_VP1_CONFIG[7] VSYNCGATED and [6] HSYNCGATED register bits. In addition, the alignment between VSYNC and HSYNC signals can be programmed via the DSS_VP1_POL_FREQ[18] ALIGN register bit.

The latch of data can be driven on the rising or falling edge of the pixel clock by setting the DSS_VP1_POL_FREQ[14] IPC register bit. The drive of the SYNC and VSYNC signals in the function of the pixel clock is done by setting the DSS_VP1_POL_FREQ[16] RF bit.

Note:

To set the pixel clock, CTRL_MMR_DPI0_CLK_CTRL[8] DPI0_CLK_CTRL_DATA_CLK_INVDIS setting should always be the same as the DSS_VP1_POL_FREQ[14] IPC setting, and CTRL_MMR_DPI0_CLK_CTRL[9] DPI0_CLK_CTRL_SYNC_CLK_INVDIS setting should always be the same as the DSS_VP1_POL_FREQ[16] RF setting.

For example, if CTRL_MMR_DPI0_CLK_CTRL[8] DPI0_CLK_CTRL_DATA_CLK_INVDIS is set to 1, DSS_VP1_POL_FREQ[14] IPC should be set to 1.

Each VP output can be configured in progressive output mode or interlaced output mode. The selection is done by writing into the bit-field DSS_VP1_CONFIG[22] OUTPUTMODEENABLE register bit. The default setting is for progressive mode. The selection can be changed only when the corresponding VP output is disabled. The configuration is independent for each VP output. It is possible to change the configuration of one of the VP outputs while the other VP is enabled.

The pixel clock for each VP output can be gated by setting the DSS_VP1_CONFIG[5] PIXELCLOCKGATED register bit.

The hold time of the pixels on the data bus is determined in clock cycles by the DSS_VP1_CONTROL[16-14] HT register field.