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时钟和计时
时钟发生器

LMK03001

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具有集成 VCO 的 1470 至 1570MHz、800FS RMS 抖动、精密时钟调节器

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数据表

LMK03001

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产品详情

Number of outputs 9 Output type LVDS Output frequency (max) (MHz) 2160 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVPECL Operating temperature range (°C) -40 to 85 Features Integrated VCO, uWire Rating Catalog
Number of outputs 9 Output type LVDS Output frequency (max) (MHz) 2160 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVPECL Operating temperature range (°C) -40 to 85 Features Integrated VCO, uWire Rating Catalog
WQFN (RHS) 48 49 mm² 7 x 7
  • Integrated VCO with Very Low Phase Noise Floor
  • Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/Hz
  • VCO Divider Values of 2 to 8 (All Divides)
  • Channel Divider Values of 1, 2 to 510 (even divides)
  • LVDS and LVPECL Clock Outputs
  • Partially Integrated Loop Filter
  • Dedicated Divider and Delay Blocks on Each Clock Output
  • Pin Compatible Family of Clocking Devices
  • 3.15 to 3.45 V Operation
  • Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
  • 200 fs RMS Clock Generator Performance (10 Hz to 20 MHz) with a Clean Input Clock

All trademarks are the property of their respective owners.

  • Integrated VCO with Very Low Phase Noise Floor
  • Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/Hz
  • VCO Divider Values of 2 to 8 (All Divides)
  • Channel Divider Values of 1, 2 to 510 (even divides)
  • LVDS and LVPECL Clock Outputs
  • Partially Integrated Loop Filter
  • Dedicated Divider and Delay Blocks on Each Clock Output
  • Pin Compatible Family of Clocking Devices
  • 3.15 to 3.45 V Operation
  • Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
  • 200 fs RMS Clock Generator Performance (10 Hz to 20 MHz) with a Clean Input Clock

All trademarks are the property of their respective owners.

The LMK03000 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.

The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO Divider to feed the various clock distribution blocks.

Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.

The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking devices in the same family.

The LMK03000 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.

The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO Divider to feed the various clock distribution blocks.

Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.

The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking devices in the same family.
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 LMK03000 Family Precision Clock Conditioner with Integrated VCO 数据表 (Rev. O) 2013年 3月 15日
应用手册 AN-1734 Using the LMK03000C to Clean Recovered Clocks (Rev. B) 2013年 4月 26日
应用手册 AN-1821 CPRI Repeater System (Rev. A) 2013年 4月 26日
应用手册 AN-1865 Frequency Synthesis and Planning for PLL Architectures (Rev. C) 2013年 4月 26日
应用手册 Selecting Amplifiers, ADCs, and Clocks for High-Performance Signal Paths 2007年 9月 13日
应用手册 Generating Precision Clocks for Time- Interleaved ADCs 2007年 8月 2日
设计指南 Clock Conditioner Owner's Manual 2006年 11月 10日

设计与开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

软件编程工具

CODELOADER — CodeLoader Device Register Programming v4.19.0

The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.

Which software do I use?

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支持的产品和硬件

支持的产品和硬件
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支持软件

CLOCKDESIGNTOOL — Clock Design Tool Software

The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)

支持的产品和硬件

支持的产品和硬件
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仿真模型

LMK03001 IBIS Model (Rev. A)

SNAM022A.ZIP (40 KB) - IBIS Model
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设计工具

CLOCK-TREE-ARCHITECT — 时钟树架构编程软件

时钟树架构是一款时钟树综合工具，可根据您的系统要求生成时钟树解决方案，从而帮助您简化设计流程。该工具从庞大的时钟产品数据库中提取数据，然后生成系统级多芯片时钟解决方案。
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模拟工具

PSPICE-FOR-TI — PSpice® for TI 设计和仿真工具

PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用，包括业内超大的模型库之一，涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库，您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案，然后再进行布局和制造，可缩短产品上市时间并降低开发成本。 

在 PSpice for TI 设计和仿真工具中，您可以搜索 TI (...)
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封装 引脚 CAD 符号、封装和 3D 模型
WQFN (RHS) 48 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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