SPRUIM2J May 2020 – May 2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
The xSPI protocol defines 1S-1S-1S mode for general backwards compatibility, and 8D-8D-8D for maximum throughput (where bit-width (1 or 8) and data rate (Single Data Rate or Double Data rate).
For 1S-1S-1S mode of operation (Bit-width =1, Single Data Rate). The Command and Address issued are 8 bits and 24 bits respectively. The Read Command that is issued is 0x0b.The frequency of operation supported is 50 MHz.
For 8D-8D-8D mode of operation (Bit-width =8, Double Data Rate). The Command and Address issued are 8 bits and 32 bits respectively. The Read Command that is issued is 0x0b or 0xee. The frequency of operation will be 25MHz for device silicon revisions that are affected by errata i2420, or 20MHz for device silicon revisions which are not affected by i2420. Please refer to device specific errata documentation for more information.
For SFDP mode ROM starts operation in 1S-1S-1S mode reads SFDP header from flash memory to get 8D-8D-8D switching sequence, Read Command, CMD Extension and Byte Order. SFDP parsing of ROM is described below and on successful parsing ROM will issue 8D-8D-8D command switching sequence and then will read the boot image in 8D-8D-8D mode with read command specified in SFDP header
Figure 4-5 xSPI Flow Chart
Figure 4-6 ROM SFDP Parser Flow