SPRUIM2J May 2020 – May 2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
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| Instance Name | Physical Address |
|---|---|
| DDR16SS0 | 0F30 A288h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PI_NO_CATR_READ | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_CATR | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_RESERVED53 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PI_FREQ_SEL_FROM_REGIF | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:25 | RESERVED | NONE | 0h | Reserved |
| 24 | PI_NO_CATR_READ | R/W | 0h | Defines how the LPDDR4 termination status is determined. 1: PI use PI_CATR to get DRAM CA Termination status. 0: PI reads DRAM MR0.OP7 to get DRAM CA Termination status. Reset Source: ctl_amod_g_rst_n |
| 23:18 | RESERVED | NONE | 0h | Reserved |
| 17:16 | PI_CATR | R/W | 0h | It indicates LP4 DRAM CA terminition ON/OFF state. Each bit corresponds to each chip select. 1:ON 0:OFF. This parameter is active when PI_NO_CATR_READ==1. When PI_NO_CATR_READ==0, this param is inactive Reset Source: ctl_amod_g_rst_n |
| 15:13 | RESERVED | NONE | 0h | Reserved |
| 12:8 | PI_RESERVED53 | R/W | 0h | Reserved |
| 7:1 | RESERVED | NONE | 0h | Reserved |
| 0 | PI_FREQ_SEL_FROM_REGIF | R/W | 0h | In non-DFI 4.0 mode, user select the frequency copies from pi_freq_change_reg_copy. Reset Source: ctl_amod_g_rst_n |