Integrated in the MCU domain: One Arm
Cortex-M4F Subsystem module. This processor core can be configured as an isolated
safety MCU or general purpose MCU.
- Cortex M4F With Memory Protection
Unit
(MPU)
- ARMv7-M
architecture
- Support for Nested Vectored
Interrupt Controller (NVIC) with 64 inputs
- Ability to execute code from
internal or external memories
- 192 KB of SRAM (I-Code)
- 64 KB of SRAM (D-Code)
- Debug Support Including:
- DAP based Debug to the
CPU Core
- Full Debug Features of
CPU Core are enabled
- Standard ITM trace
- CTM Cross Trigger
- ETM Trace Support
- Fault Detection and
Correction:
- SECDED ECC protection on
I-CODE
- SECDED ECC protection on
D-CODE
- Fault Error Interrupt
Output