SPRUIM2J May 2020 – May 2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
The PRU_ICSSG UART0 receiver section includes a receiver shift register (RSR), that is not memory mapped, and a receiver buffer register (RBR), memory mapped as the register ICSS_G_PR1_ICSS_UART_UART_SLV_RBR[7-0] DATA bitfield. When the PRU_ICSSG UART0 is in the FIFO mode, RBR is a 16-byte FIFO. Receiver section control is a function of the PRU_ICSSG UART0 line control register - ICSS_G_PR1_ICSS_UART_UART_SLV_LCR. Based on the settings chosen in this register, the PRU_ICSSG UART0 receiver accepts the following from the transmitting device:
RSR receives the data bits from the UART0_RXD pin. Then RSR concatenates the data bits and moves the resulting value into RBR (or the receiver FIFO), accessible in the RBR_TBR[7-0] RBR_DATA register bitfield. The PRU_ICSSG UART0 also stores three bits of error status information next to each received character, to record a parity error, framing error, or break.
In the non-FIFO mode, when a character is placed in RBR and the receiver data available interrupt is enabled in the interrupt enable register - ICSS_G_PR1_ICSS_UART_UART_SLV_IER[0] ERBI, an interrupt is generated. This interrupt is cleared when the character is read from RBR. In the FIFO mode, the interrupt is generated when the FIFO is filled to the trigger level selected in the FIFO control MSB part of the register ICSS_G_PR1_ICSS_UART_UART_SLV_IIR, and it is cleared when the FIFO contents drop below the trigger level.