Figure 12-146 shows the integration of the SERDES0 module in the device.
Table 12-209 through Table 12-212 summarizes the integration of SerDes in device MAIN domain.
Table 12-209 SerDes Integration
Attributes
| Module Instance |
Power Sleep
Controller |
Power Domain |
Module Domain |
Interconnect |
| SERDES0 |
PSC0 |
PD0 |
LPSC15 |
CBASS0 |
Table 12-210 SerDes Clocks
| Module Instance |
Module Clock Input |
Source Clock Signal |
Source |
Description |
| SERDES0 | SERDES0_ICLK | MAIN_SYSCLK0/4 | PLL_CTRL0 | VBUS interface clock |
| CMN_REFCLK_INT | WKUP_HFOSC0_CLKOUT | WKUP_HFOSC0 | Internal reference clock from device sources. Software selectable. See Section 12.2.3.3.1.2 |
| | HFOSC1_CLKOUT | HFOSC1 |
| | MAIN_PLL0_HSDIV8_CLKOUT | PLL0 |
| | MAIN_PLL2_HSDIV4_CLKOUT | PLL2 |
Table 12-211 SerDes Resets
| Module Instance |
Module Reset Input |
Source Reset Signal |
Source |
Description |
| SERDES0 |
SERDES0_RST |
MOD_G_RST |
LPSC15 |
Serdes LPSC reset |
Table 12-212 SerDes Hardware
Requests
| Module Instance |
Module Interrupt Signal |
Destination Interrupt Input |
Destination |
Description |
Type |
| SERDES0 |
PHY_PWR_TIMEOUT_LVL_0 |
GICSS0_SPI_IN_142 |
GICSS0 |
Lane power timeout interrupt |
Level |
|
|
R5FSS0_CORE0_INTR_IN_180 |
R5FSS0_CORE0 |
|
|
|
|
R5FSS0_CORE1_INTR_IN_180 |
R5FSS0_CORE1 |
|
|
|
|
R5FSS1_CORE0_INTR_IN_180 |
R5FSS1_CORE0 |
|
|
|
|
R5FSS1_CORE1_INTR_IN_180 |
R5FSS1_CORE1 |
|
|
Table 12-213 SerDes DMA Events
| Module Instance |
Module DMA Event |
Destination DMA Event Input |
Destination |
Description |
Type |
| SERDES0 |
- |
- |
- |
No PDMA channels to external DMA engines |
- |