SPRUIM2J May 2020 – May 2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
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| Instance Name | Physical Address |
|---|---|
| DDR16SS0 | 0F30 A280h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_TREFBW_THR | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PI_TREFBW_THR | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:9 | RESERVED | NONE | 0h | Reserved |
| 8:0 | PI_TREFBW_THR | R/W | 0h | Threshold value to control the AREF command interval. When the number of pending AREF is over this value, the interval is expanded to be tREF/8. Reset Source: ctl_amod_g_rst_n |